MC9S08DN60F1CLF datasheet(69/356 Pages) FREESCALE

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Chapter 5 Resets, Interrupts, and General System Control

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

comprised of a power-on reset (POR) circuit and a LVD circuit with trip voltages for warning and

detection. The LVD circuit is enabled when LVDE in SPMSC1 is set to 1. The LVD is disabled upon

entering any of the stop modes unless LVDSE is set in SPMSC1. If LVDSE and LVDE are both set, then

the MCU cannot enter stop2 (it will enter stop3 instead), and the current consumption in stop3 with the

LVD enabled will be higher.

5.6.1

Power-On Reset Operation

When power is initially applied to the MCU, or when the supply voltage drops below the power-on reset

rearm voltage level, VPOR, the POR circuit will cause a reset condition. As the supply voltage rises, the

LVD circuit will hold the MCU in reset until the supply has risen above the low-voltage detection low

threshold, VLVDL. Both the POR bit and the LVD bit in SRS are set following a POR.

5.6.2

Low-Voltage Detection (LVD) Reset Operation

The LVD can be conﬁgured to generate a reset upon detection of a low-voltage condition by setting

LVDRE to 1. The low-voltage detection threshold is determined by the LVDV bit. After an LVD reset has

occurred, the LVD system will hold the MCU in reset until the supply voltage has risen above the

low-voltage detection threshold. The LVD bit in the SRS register is set following either an LVD reset or

POR.

5.6.3

Low-Voltage Warning (LVW) Interrupt Operation

The LVD system has a low-voltage warning ﬂag to indicate to the user that the supply voltage is

approaching the low-voltage condition. When a low-voltage warning condition is detected and is

conﬁgured for interrupt operation (LVWIE set to 1), LVWF in SPMSC1 will be set and an LVW interrupt

request will occur.

5.7

MCLK Output

The PTA0 pin is shared with the MCLK clock output. If the MCSEL bits are all zeroes, the MCLK clock

is disabled. Setting any of the MCSEL bits causes the PTA0 pin to output a divided version of the internal

MCU bus clock regardless of the state of the port data direction control bit for the pin. The divide ratio is

determined by the MCSEL bits. The slew rate and drive strength for the pin are controlled by PTASE0 and

PTADS0, respectively. The maximum clock output frequency is limited if slew rate control is enabled, see

the electrical speciﬁcations for the maximum frequency under different conditions.

MC9S08DN60F1CLF Datasheet(PDF) 69 Page - Freescale Semiconductor, Inc