26HS01GTAM03 datasheet(136/166 Pages) INFINEON

136 / 166 page

Datasheet

136 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Transaction table

Command Definitions Legend

X = Don't care

RA = Address of the memory to be read

RD = Data read from location RA during read operation

PA = Address of the memory location to be programmed

PD = Data to be programmed at location PA

SA = Address of the sector selected. Address bits AMAX-A17 for 256KB sectors and AMAX-A11 for 4KB parameter sectors uniquely select any sector.

WBL = Write Buffer Location. The address must be within the same Line.

WC = Word Count is the number of write buffer locations to load minus 1.

PWAx = Password address for word0 = 00h, word1 = 01h, word2 = 02h, and word3 = 03h

PWDx = Password data word0, word1, word2, and word3

EFPRx = Infineon Endurance Flex architecture pointer address registers 0, 1, 2, 3, 4

DA = Die Address (DA[1:0] = 00b for all the devices)

Notes

35. All values are in hexadecimal. All addresses reference 16-bit words.

36. Except for the following, all bus cycles are write cycle: read cycle during Read, ID Read (Manufacturing ID / Device ID), Indicator Bits, SSR Read, SSR

Lock Read, and 2nd cycle of Status Register Read.

37. Data bits DQ15-DQ8 are ‘don't care’ in command sequences, except for RD, PD, WC and PWD.

38. Address bits AMAX-A11 are ‘don't care’ for unlock and command cycles, unless SA or PA required. (AMAX is the Highest Address pin.)

39. No unlock or command cycles required when reading array data.

40. The Reset command is required to return to reading array data when device is in ID-SFDP (Autoselect) mode.

41. Command is valid when device is ready to read array data or when device is in ID-SFDP mode.

42. The system can read and program / program suspend in non-erasing sectors, or enter the ID-SFDP ASO, when in the Erase Suspend mode. The Erase

Suspend command is valid only during a sector erase operation.

43. The Erase Resume / Program Resume command is valid only during the Erase Suspend / Program Suspend modes.

44. Issue this command sequence to return to READ mode after detecting device is in a Write-to-Buffer-Abort state. Note that the full command sequence

is required if resetting out of ABORT.

45. The Exit command returns the device to reading the array.

46. For PWDx, only one portion of the password can be programmed per each ‘A0’ command. Portions of the password must be programmed in sequential

order (PWD0-PWD3).

47. All ASP Register bits are OTP. The program state = 0 and the erase state = 1. Both the Persistent Protection Mode Lock Bit and the Password Protection

Mode Lock Bit cannot be programmed at the same time or the ASPR Register Bits Program operation aborts and returns the device to Read mode. ASPR

48. If any of the Entry commands was issued, an Exit command must be issued to reset the device into Read mode.

49. Bit 0 = 0 indicates the Protected State, Bit 0 = 1 indicates the Unprotected State - Bits 1 through 15 are all 0s for Protected and all 1s for Unprotected.

The sector address for DYB set, DYB clear, or PPB Program command may be any location within the sector; the lower order bits of the sector address

are “don't care”. Note that PPB Program command gets aborted if bits 1 through 15 are not all 0s.

50. Data out during a Register Read transaction is only valid during the first word output by the device. Subsequent data values output if CK/CK# continue

to toggle while CS# remains Low are undefined.

51. Data out during a SA Protection Status Read indicates whether the indicated sector is protected in bits 0-2.

Bit 0 – Indicates whether the indicated sector is protected (0 = protected, 1 = unprotected).

Bit 1 – Protected using the sector’s DYB bit (0 = protected, 1 = unprotected).

Bit 2 – Protected using the sector’s PPB bit (0 = protected, 1 = unprotected).

Bits 3 through 15 are all 1s.

52. The smaller parameter-sectors need to include A[16:11] as part of the address identifying the target parameter-sector during erase and program

command sequences.

53. Reset / ASO Exit behavior

54. Clears SR0[5,4,3,1,0] when the device not busy or in the middle of a command sequence.

Clears SR0[5,4,3,1,0] when the device not busy or in an ASO.

55. The device will return to Standby mode once CS# goes HIGH if an illegal command sequence is entered.

56. Reset, ASO Exit, Status Register Read and Status Register Clear commands are globally applicable in all ASOs.

57. Wrap feature is not available in AutoBoot mode when Reading from the memory array.

58. Programming Power-On-Reset Timer Register and Nonvolatile Configuration registers should never be suspended. Suspending will produce indeter-

minate results and a hardware reset will be required to return to standby mode.

59. Enter SPI mode command sequence must be followed by a Read Any Register command (RDAR) in SPI mode for proper transitioning from HYPERBUS™

to SPI interfaces.

26HS01GTAM03 Datasheet(PDF) 136 Page - Infineon Technologies AG

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