26HS01GTAM03 datasheet(139/166 Pages) INFINEON

139 / 166 page

Advanced

Sector

Protectio

RDDYB_4_0

Read Dynamic Protection Bit transaction reads the contents

of the DYB Access Register.

(CMD)

ADDR

[31:24]

ADDR

[23:16]

ADDR

[15:8]

ADDR

[7:0]

---

Figure 11

166

WRDYB_4_1 Write Dynamic Protection Bit transaction writes to the DYB

Access Register.

WRENB_0_0

(CMD)

ADDR

[31:24]

ADDR

[23:16]

ADDR

[15:8]

ADDR

[7:0]

Input

Data1

[7:0]

Input

Data2

[7:0]

(Conti

nue)

Figure 8

RDPPB_4_0

Read Persistent Protection Bit transaction reads the contents

of the PPB Access Register.

(CMD)

ADDR

[31:24]

ADDR

[23:16]

ADDR

[15:8]

ADDR

[7:0]

---

Figure 11

PRPPB_4_0

Program Persistent Protection Bit transaction programs /

writes the PPB Register to enable the sector protection.

WRENB_0_0

(CMD)

ADDR

[31:24]

ADDR

[23:16]

ADDR

[15:8]

ADDR

[7:0]

---

Figure 6

ERPPB_0_0

Erase Persistent Protection Bit transaction sets all persistent

protection bits to 1.

WRENB_0_0

(CMD)

---

Figure 5

N/A

WRPLB_0_0 Write PPB Protection Lock Bit transaction clears the PPB Lock

to 0.

WRENB_0_0

(CMD)

---

RDPLB_0_0

Read Password Protection Mode Lock Bit transaction shifts

out the 8-bit PPB Lock Register contents with MSb first.

(CMD)

---

Figure 10

PWDUL_0_1

Password Unlock transaction sends the 64-bit password to

flash device. If the supplied password does not match the

hidden password in the Password Register, the device is locked

and only a hardware reset or POR will return the device to

standby state, ready for new transactions such as a retry of the

PWDUL_0_1. If the password does match, the PPB Lock bit is

set to 1.

(CMD)

Passwor

d [7:0]

Passwor

d [15:8]

Passwor

d [23:16]

Passwor

d [31:24]

Passw

ord

[39:32

]

Passw

ord

[47:40

]

Passw

ord

[55:48

]

Passw

ord

[63:56]

Figure 9

Reset

SRSTE_0_0

Software Reset Enable command is required immediately

before a SFRST_0_0 transaction.

(CMD)

---

Figure 5

SFRST_0_0

Software Reset transaction restores the device to its initial

power up state, by reloading Volatile registers from nonvolatile

default values.

SRSTE_0_0

(CMD)

---

Deep

Power

Down

ENDPD_0_0 Enter Deep Power Down Mode transaction shifts device in the

lowest power consumption mode.

(CMD)

---

Table 122

SPI (1S-1S-1S) transaction table (Continued)

Function

Transaction

name

Description

Prerequisite

transaction

Byte1

(Hex)

Byte 2

(Hex)

Byte 3

(Hex)

Byte 4

(Hex)

Byte 5

(Hex)

Byte6

(Hex)

Byte7

(Hex)

Byte8

(Hex)

Byte 9

(Hex)

Transaction

format

Max

frequency

(MHz)

Address

length

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