26HS01GTAM03 datasheet(137/166 Pages) INFINEON

137 / 166 page

6.2

Legacy (x1) SPI transaction table

Table 122

SPI (1S-1S-1S) transaction table

Function

Transaction

name

Description

Prerequisite

transaction

Byte1

(Hex)

Byte 2

(Hex)

Byte 3

(Hex)

Byte 4

(Hex)

Byte 5

(Hex)

Byte6

(Hex)

Byte7

(Hex)

Byte8

(Hex)

Byte 9

(Hex)

Transaction

format

Max

frequency

(MHz)

Address

length

Read

Device ID

RDIDN_0_0

Read manufacturer and device identification transaction

provides read access to manufacturer and device identifi-

cation.

(CMD)

---

Figure 10

166

N/A

RSFDP_3_0

Read JEDEC Serial Flash Discoverable Parameters trans-

action sequentially accesses the Serial Flash Discovery Param-

eters (SFDP).

(CMD)

(ADDR)

---

Figure 11

156

RDUID_0_0

Read Unique ID accesses a factory programmed

64-bit number which is unique to each device.

(CMD)

---

Figure 10

166

N/A

Access

RDSR1_0_0

Read Status Register 1 transaction allows the Status Register

1 contents to be read from DQ1/SO.

(CMD)

---

RDSR2_0_0

Read Status Register-2 transaction allows the Status

(CMD)

---

RDARG_C_0 Read Any Register transaction provides a way to read all

addressed nonvolatile and volatile device registers.

(CMD)

ADDR

[23:16]

ADDR

[15:8]

ADDR

[7:0]

---

Figure 11

ADDR

[31:24]

ADDR

[23:16]

ADDR

[15:8]

ADDR

[7:0]

---

WRENB_0_0

Write Enable sets the Write Enable Latch bit of the Status

tions.

(CMD)

---

Figure 5

N/A

WRDIS_0_0

Write Disable sets the Write Enable Latch bit of the Status

execution.

(CMD)

---

WRARG_C_1 Write Any Register transaction provides a way to write all

addressed Nonvolatile and Volatile Device registers.

WRENB_0_0

(CMD)

ADDR

[23:16]

ADDR

[15:8]

ADDR

[7:0]

Input

Data [7:0]

---

Figure 8

ADDR

[31:24]

ADDR

[23:16]

ADDR

[15:8]

ADDR

[7:0]

Input

Data

[7:0]

CLPEF_0_0

Clear Program and Erase Failure Flags transaction resets

STR1V[5] (Erase failure flag) and STR1V[6] (Program failure

flag).

(CMD)

---

Figure 5

N/A

ECC

RDECC_4_0

Read ECC Status is used to determine the ECC status of the

addressed data unit.

(CMD)

ADDR

[31:24]

ADDR

[23:16]

ADDR

[15:8]

ADDR

[7:0]

---

Figure 11

CLECC_0_0

Clear ECC Status Register transaction resets ECC Status

(1-bit ECC Correction), Address Trap Register, and ECC

Detection Counter.

(CMD)

---

Figure 5

N/A

CRC

DICHK_4_1

Data Integrity Check transaction causes the device to perform

a Data Integrity Check over a user defined address range.

(CMD)

Start

ADDR

[31:24]

Start

ADDR

[23:16]

Start

ADDR

[15:8]

Start

ADDR

[7:0]

End

ADDR

[31:24

]

End

ADDR

[23:16

]

End

ADDR

[15:8]

End

ADDR

[7:0]

Figure 7

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