26HS01GTAM03 datasheet(145/166 Pages) INFINEON

145 / 166 page

Datasheet

145 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Timing characteristics

Table 129

Timing characteristics[70]

Symbol

Parameter

Min

Typ

Max

Unit

Reference

figure

HYPERBUS™

fCK

CK Clock Frequency for HYPERBUS™ mode transactions using

DS (HS-T)

–200

MHz

–

CK Clock Frequency for HYPERBUS™ mode transactions using

DS (HL-T)

–166

pCK

CK Clock Period

1/fCK

–

∞

Figure 56

tCH

Clock High Time

45% pCK

–

55% pCK

Figure 59

tCL

Clock Low Time

–

tCS

CS# High Time (Read transactions)

7.5

–

Figure 62

CS# High Time (CRC ASO: including ASO entry and exit Config-

uration Register Load Program)

–

tCSS

CS# Active Setup Time (relative to CK)

–

tCSH0

CS# Active Hold Time (relative to CK in Mode 0)

–

tSU

HS-T Data Setup Time (all VCC)0.5

–

HL-T Data Setup Time (all VCC)0.6

–

tHD

HL-T Data Hold Time (all VCC)0.6

–

HS-T Data Hold Time (all VCC)0.5

–

tV[71]

Clock Low to Output Valid (15pF Loading) (HS-T)

–5.45

Figure 63

Clock Low to Output Valid (15pF Loading) (HL-T)

–

7.25

tCKDS

DS Valid (HS-T)

–

5.45

DS Valid (HL-T)

–

7.25

tDSS[72]

DS transition to Data Valid

0.4

–

0.4

tDSH[72]

DS transition to Data Invalid

0.4

–

0.4

tDIS[70]

CS# Inactive to Output Disable Time (HS-T)

–

6.00

Figure 63

CS# Inactive to Output Disable Time (HL-T)

–

7.50

tDSZ

CS# Inactive to DS Disable Time (HS-T)

–

6.00

CS# Inactive to DS Disable Time (HL-T)

–

7.50

tIO_SKEW[72]

Data Skew (First Data Bit to Last Data Bit)

–

0.4

–

SPI SDR

fCK

CK Clock Frequency

–

166

MHz

–

pCK

CK Clock Period

1/ fCK

–

∞

Figure 56

tCH

Clock High Time

45% pCK

–55% pCK

Figure 59

tCL

Clock Low Time

45% pCK

–55% pCK

tCS

CS# High Time (Read transactions)

–

Figure 60 /

Figure 61

CS# High Time Between Transactions (aborted commands)

–

CS# High Time (Program / Erase transactions)

–

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