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26HS01GTAM03 Datasheet(PDF) 148 Page - Infineon Technologies AG |
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26HS01GTAM03 Datasheet(HTML) 148 Page - Infineon Technologies AG |
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148 / 166 page  Datasheet 148 of 166 002-12337 Rev. *Y 2022-01-18 256Mb/512Mb/1Gb SEMPER™ Flash HYPERBUS™ interface, 1.8V/3.0V Timing characteristics 8.1 Timing waveforms 8.1.1 Key to timing waveform Figure 55 Waveform element meanings 8.1.2 Timing reference levels Figure 56 Input timing reference levels Figure 57 SDR output timing reference level Figure 58 DDR output timing reference level Valid at logic High or Low High Impedance Any change permitted Logic High Logic Low Valid at logic High or Low High Impedance Changing, state unknown Logic High Logic Low Input Symbol Output pCK tSU tSU VCCQ VSSQ VIH(ac) VIL(ac) VCCQ VSSQ CK DQ[7:0] tDRT tDFT Timing Reference Level PCK VCCQ VSSQ CK tV tV VCCQ VSSQ DQ[7:0] VOH(ac) VOL(ac) Timing Reference Level PCK DS VOH(ac) VOL(ac) VCCQ VSSQ DQ[7:0] tDSS tDSH VCCQ VSSQ Timing Reference Level |
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