26HS01GTAM03 datasheet(146/166 Pages) INFINEON

146 / 166 page

Datasheet

146 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Timing characteristics

tCSS

CS# Active Setup Time relative to CK (fCK  50MHz / fCK >

50MHz)

5/4

–

Figure 60

tCSH0

CS# Active Hold Time (relative to CK in Mode 0)

–

tCSH3

CS# Active Hold Time (relative to CK in Mode 3)

–

Figure 60

tSU

Data Setup Time (all VCC) (fCK 50MHz / fCK > 50MHz)

5 / 2

–

tHD

Data Hold Time (all VCC) (fCK 50MHz / fCK > 50MHz)

5 / 2

–

Clock Low to Output Valid

(15pF Loading, 3.0V  3.6V, 30  Output Impedance) (HL-T)

2–

6.5

Figure 61

Clock Low to Output Valid (30pF Loading) (HS-T)

–

Clock Low to Output Valid (30pF Loading) (HL-T)

–

Clock Low to Output Valid (15pF Loading) (HS-T)

–

Clock Low to Output Valid (15pF Loading) (HL-T)

–

tHO

Output Hold Time

1.5

–

tDIS

Output Disable Time (HS-T)

–

Output Disable Time (HL-T)

–

7.50

Power Up / Power Down Timing

tPU

VCC(min) to Read operation

(HL256T / HS256T)

(HL512T / HS512T)

(HL01GT / HS01GT)

––

550 / 600

450 / 500

500 / 500

µs

Figure 47

tPD

VCC(Low) time

–

Figure 48

tVR[79]

VCC / VCCQ Power Up ramp rate

–

µs/V

Figure 49

tVF

VCC / VCCQ Power Down ramp rate

–

Figure 64

Deep Power Down Mode Timing

tENTDPD[79]

Time to Enter DPD mode

–

µs

–

tEXTDPD

Time to Exit DPD mode

(HL256T / HS256T)

(HL512T / HS512T)

(HL01GT / HS01GT)

––

520 / 570

380 / 430

430 / 430

Figure 46

tCSDPD

Chip Select Pulse Width to Exit DPD

0.02

–

Reset Timing[74, 75]

tRS

Reset Setup - RESET# High before CS# Low

–

Figure 39

tRH

Reset Pulse Hold - RESET# Low to CS# Low

(HL256T / HS256T)

(HL512T / HS512T)

(HL01GT / HS01GT)

550 / 600

450 / 500

500 / 500

––

µs

tRP

RESET# Pulse Width

200

–

tSR

Internal Device Reset from Software Reset Transaction

(256T / 512T / 01GT)

–

90 / 83 / 83

µs

–

CS# Signaling Reset Timing

tCSLW

Chip Select Low

500

–

Figure 44

tCSHG

Chip Select High

500

–

tRESET

Internal device reset (HL512T / HS512T / HL01GT / HS01GT)

–

450 / 500 /

500 / 500

µs

tSUJ

Data in Setup Time (w.r.t CS#)

–

tHDJ

Data in Hold Time (w.r.t CS#)

–

Embedded Algorithm (Erase, Program and Data Integrity Check) Performance[76, 77, 78, 79]

Nonvolatile Register Write Time

–

357.5

–

tPP

256B Page Programming (4KB Sector / 256KB Sector)

–

430 / 480

2175 / 1700

µs

–

512B Page Programming (4KB Sector / 256KB Sector)

–

680 / 570

2175 / 1700

Table 129

Timing characteristics[70] (Continued)

Symbol

Parameter

Min

Typ

Max

Unit

Reference

figure

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