26HS01GTAM03 datasheet(147/166 Pages) INFINEON

147 / 166 page

Datasheet

147 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Timing characteristics

Notes

70. Applicable across all operating temperature options.

71. Full VCC range and CL = 15pF.

72. Output HI-Z is defined as the point where data is no longer driven.

73. If Reset# is asserted during the end of tPU, the device will remain in the reset state and tRH will determine when CS# may go Low.

74. Sum of tRP and tRH must be equal to or greater than tRPH.

75. Typical program and erase times assume the following conditions: 25°C, VCC = 1.8V and 3.0V; 10,000 cycles; checkerboard data pattern.

76. The programming time for any OTP programming transaction is the same as tPP. This includes PRSSR_4_1.

77. The programming time for the PRPPB_4_0 transaction is the same as tPP. The erase time for ERPPB_0_0 transaction is the same as tSE.

78. Values are guaranteed by characterization and not 100% tested in production.

79. Guaranteed by design.

80. The Joint Electron Device Engineering Council (JEDEC) standard JESD22-A117 defines the procedural requirements for performing valid endurance

and retention tests based on a qualification specification. This methodology is intended to determine the ability of a flash device to sustain repeated

data changes without failure (program/erase endurance) and to retain data for the expected life (data retention). Endurance and retention qualification

specifications are specified in JESD47 or may be developed using knowledge-based methods as in JESD94.

tSE

Sector Erase Time (4KB physical sectors)

–

335

–

Sector Erase Time (256KB Infineon Endurance Flex archi-

tecture disabled)

–

773

2677

Sector Erase Time (256KB Infineon Endurance Flex archi-

tecture enabled)

–

773

5869

tBE

Chip Erase Time (256Mb)

–

101

348

sec

–

Chip Erase Time (512Mb)

–

201

696

Chip Erase Time (1Gb)

–

398

1381

tEES

Evaluate Erase Status Time for 4KB physical sectors

(HL256T / HS256T)

(HL512T / HS512T)

(HL01GT / HS01GT)

–

76 / 76

51 / 51

53 / 56

µs

–

Evaluate Erase Status Time for 256KB physical sectors

(HL256T / HS256T)

(HL512T / HS512T)

(HL01GT / HS01GT)

–

tDIC_SETUP

Data Integrity Check Calculation Setup Time

(256T / 512T / 01GT)

–

50 / 50 / 17

–

µs

–

tDIC_RATES

Data Integrity Check Calculation Rate (Calculation rate over a

large (>1024-byte) block of data) (HL512T / HS512T / HL01GT /

HS01GT)

55 / 55 / 56 /

–

MBps

–

tSEC

Sector Erase Count Time

(HL256T / HS256T)

(HL512T / HS512T)

(HL01GT / HS01GT)

–55

87 / 87

63 / 63

70 / 70

µs

–

tBEC1

Blank Check single 256KB sector

–

tBEC2

Blank Check single 4KB sector

–

tPSWD

Setting the PPB Lock bit after the valid 64-bit password is given

to the device

100

120

µs

–

Program, Erase or Data Integrity Check Suspend/Resume Timing

tPEDS

Program/Erase/Data Integrity Check Suspend

–

µs

–

tPEDRS

Program/Erase/Data Integrity Check Resume to next

Program/Erase/Data Integrity Check Suspend

(256T / 512T / 01GT)

250 / – / –

100 / 100 /

100

–

Table 129

Timing characteristics[70] (Continued)

Symbol

Parameter

Min

Typ

Max

Unit

Reference

figure

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