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ST10F280 Datasheet(PDF) 72 Page - STMicroelectronics

Part # ST10F280
Description  16-bit MCU with MAC unit, 512 Kbyte Flash memory and 18 Kbyte RAM
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F280 Datasheet(HTML) 72 Page - STMicroelectronics

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Interrupt system
ST10F280
72/239
Doc ID 8673 Rev. 3
Hardware traps are exceptions or error conditions that arise during run-time. They cause
immediate non-maskable system reaction similar to a standard interrupt service (branching
to a dedicated vector table location).
The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag
register (TFR). Except when another higher prioritized trap service is in progress, a
hardware trap will interrupt any other program execution. Hardware trap services cannot not
be interrupted by standard interrupt or by PEC interrupts.
8.3
Interrupt Control Registers
All interrupt control registers are identically organized. The lower 8 bit of an interrupt control
register contain the complete interrupt status information of the associated source, which is
required during one round of prioritization, the upper 8 bit of the respective register are
reserved. All interrupt control registers are bit-addressable and all bit can be read or written
via software.
This allows each interrupt source to be programmed or modified with just one instruction.
When accessing interrupt control registers through instructions which operate on Word data
types, their upper 8 bit (15...8) will return zeros, when read, and will discard written data.
The layout of the Interrupt Control registers shown below applies to each xxIC register,
where xx stands for the mnemonic for the respective source.
ASC0 Receive
S0RIR
S0RIE
S0RINT
00’00ACh
2Bh
ASC0 Error
S0EIR
S0EIE
S0EINT
00’00B0h
2Ch
SSC Transmit
SCTIR
SCTIE
SCTINT
00’00B4h
2Dh
SSC Receive
SCRIR
SCRIE
SCRINT
00’00B8h
2Eh
SSC Error
SCEIR
SCEIE
SCEINT
00’00BCh
2Fh
PWM Channel 0...3
PWMIR
PWMIE
PWMINT
00’00FCh
3Fh
CAN1 Interface
XP0IR
XP0IE
XP0INT
00’0100h
40h
CAN2 Interface
XP1IR
XP1IE
XP1INT
00’0104h
41h
XPWM
XP2IR
XP2IE
XP2INT
00’0108h
42h
PLL Unlock/OWD
XP3IR
XP3IE
XP3INT
00’010Ch
43h
Table 8.
Interrupt sources (continued)
Source of Interrupt or
PEC service request
Request
flag
Enable
flag
Interrupt
vector
Vector
location
Trap
number


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