ST10F280_12 datasheet(78/239 Pages) STMICROELECTRONICS

78 / 239 page

General purpose timer unit

ST10F280

78/239

Doc ID 8673 Rev. 3

General purpose timer unit

The GPT unit is a flexible multifunctional timer/counter structure which is used for time

related tasks such as event timing and counting, pulse width and duty cycle measurements,

pulse generation, or pulse multiplication. The GPT unit contains five 16-bit timers organized

into two separate modules GPT1 and GPT2. Each timer in each module may operate

independently in several different modes, or may be concatenated with another timer of the

same module.

10.1

GPT1

Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually for

one of four basic modes of operation: timer, gated timer, counter mode and incremental

interface mode.

In timer mode, the input clock for a timer is derived from the CPU clock, divided by a

programmable prescaler.

In counter mode, the timer is clocked in reference to external events.

Pulse width or duty cycle measurement is supported in gated timer mode where the

operation of a timer is controlled by the ‘gate’ level on an external input pin. For these

purposes, each timer has one associated port pin (TxIN) which serves as gate or clock

input.

Table 12 lists the timer input frequencies, resolution and periods for each pre-scaler option

at 40MHz CPU clock. This also applies to the Gated Timer Mode of T3 and to the auxiliary

timers T2 and T4 in Timer and Gated Timer Mode. The count direction (up/down) for each

timer is programmable by software or may be altered dynamically by an external signal on a

port pin (TxEUD).

In Incremental Interface Mode, the GPT1 timers (T2, T3, T4) can be directly connected to

the incremental position sensor signals A and B by their respective inputs TxIN and TxEUD.

Direction and count signals are internally derived from these two input signals so that the

contents of the respective timer Tx corresponds to the sensor position. The third position

sensor signal TOP0 can be connected to an interrupt input.

Timer T3 has output toggle latches (TxOTL) which changes state on each timer over flow /

underflow. The state of this latch may be output on port pins (TxOUT) for time out monitoring

of external hardware components, or may be used internally to clock timers T2 and T4 for

high resolution of long duration measurements.

In addition to their basic operating modes, timers T2 and T4 may be configured as reload or

capture registers for timer T3. When used as capture or reload registers, timers T2 and T4

are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at

their associated input pins (TxIN).

Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or

by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are

configured to alternately reload T3 on opposite state transitions of T3OTL with the low and

high times of a PWM signal, this signal can be constantly generated without software

intervention.

ST10F280 Datasheet(PDF) 78 Page - STMicroelectronics

ST10F280 Datasheet(HTML) 78 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL