ST10F280_12 datasheet(100/239 Pages) STMICROELECTRONICS

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Parallel ports

ST10F280

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Doc ID 8673 Rev. 3

To determine the appropriate level of the port output latches check how the alternate data

output is combined with the respective port latch output.

There is one basic structure for all port lines with only an alternate input function. Port lines

with only an alternate output function, however, have different structures due to the way the

direction of the pin is switched and depending on whether the pin is accessible by the user

software or not in the alternate function mode.

All port lines that are not used for these alternate functions may be used as general purpose

I/O lines. When using port pins for general purpose output, the initial output value should be

written to the port latch prior to enabling the output drivers, in order to avoid undesired

transitions on the output pins. This applies to single pins as well as to pin groups (see

examples below).

SINGLE_BIT: BSET P4.7

; Initial output level is "high"

BSET DP4.7

; Switch on the output driver

BIT_GROUP: BFLDH P4, #24H, #24H ; Initial output level is "high"

BFLDH DP4, #24H, #24H

; Switch on the output drivers

Note:

When using several BSET pairs to control more pins of one port, these pairs must be

separated by instructions, which do not reference the respective port (see “Particular

Pipeline Effects” in Chapter 6: Central Processing Unit (CPU)).

12.2

Port 0

The two 8-bit ports P0H and P0L represent the higher and lower part of PORT0,

respectively. Both halves of PORT0 can be written (e.g. via a PEC transfer) without effecting

the other half.

If this port is used for general purpose I/O, the direction of each line can be configured via

the corresponding direction registers DP0H and DP0L.

ST10F280 Datasheet(PDF) 100 Page - STMicroelectronics