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ST10F280 Datasheet(PDF) 80 Page - STMicroelectronics |
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ST10F280 Datasheet(HTML) 80 Page - STMicroelectronics |
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80 / 239 page  General purpose timer unit ST10F280 80/239 Doc ID 8673 Rev. 3 The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3 inputs T3IN and/or T3EUD. This is advantageous when T3 operates in Incremental Interface Mode. Table 13 lists the timer input frequencies, resolution and periods for each pre-scaler option at 40MHz CPU clock. This also applies to the Gated Timer Mode of T6 and to the auxiliary timer T5 in Timer and Gated Timer Mode. Figure 16. Block diagram of GPT2 Table 13. GPT2 timer input frequencies, resolution and period fCPU = 40MHz Timer input selection T5I / T6I 000b 001b 010b 011b 100b 101b 110b 111b Pre-scaler factor 4 8 16 32 64 128 256 512 Input Freq 10MHz 5MHz 2.5MHz 1.25MHz 625kHz 312.5kHz 156.25kHz 78.125kHz Resolution 100ns 200ns 400ns 0.8µs 1.6µs 3.2µs 6.4µs 12.8µs Period maximum 6.55ms 13.1ms 26.2ms 52.4ms 104.8ms 209.7ms 419.4ms 838.9ms |
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