ST10F280_12 datasheet(90/239 Pages) STMICROELECTRONICS

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PWM module

ST10F280

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Doc ID 8673 Rev. 3

XPWMCON1

Address:

0xEC02h

Reset:

0x0000h

Type:

R/W

channels. The basic operating mode for each channel (standard = edge aligned, or

symmetrical = center aligned PWM mode) is selected by the mode bits XPMx. Burst mode

(channels 0 and 1) and single shot mode (channel 2 or 3) are selected by separate control

bits. The output signal of each XPWM channel is individually enabled by bit PENx. If the

output is not enabled the respective pin can only be used to generate an interrupt request.

Note: This register is not bit-addressable.

11.2.4

Interrupt request generation

Each of the four channels of the XPWM module can generate an individual interrupt

request. Each of these “channel interrupts” can activate the common “module interrupt”,

which actually interrupts the CPU. This common module interrupt is controlled by the XPWM

Module Interrupt Control register XP2IC(Xperipherals 2 control register). The interrupt

service routine can determine the active channel interrupt(s) from the channel specific

interrupt request flags PIRx in register XPWMCON0. The interrupt request flag PIRx of a

channel is set at the beginning of a new PWM cycle, i.e. upon loading the shadow registers.

This indicates that registers XPPx and XPWx are now ready to receive a new value. If a

channel interrupt is enabled via its respective PIEx bit, also the common interrupt request

flag XP2IR in register XP2IC is set, provided that it is enabled via the common interrupt

enable bit XP2IE.

Note:

The channel interrupt request flags (PIRx in register XPWMCON0) are not automatically

cleared by hardware upon entry into the interrupt service routine, so they must be cleared

via software. The module interrupt request flag XP2IR is cleared by hardware upon entry

into the service routine, regardless of how many channel interrupts were active. However, it

PS3

PS2

PB01

PM3

PM2

PM1

PM0

PEN3

PEN2

PEN1

PEN0

R/W

PENx XPWM Channel x Output Enable Bit

0: Channel x output signal disabled, generate interrupt only

1: Channel x output signal enabled

PMx XPWM Channel x Mode Control Bit

0: Channel x operates in mode 0, edge aligned PWM

1: Channel x operates in mode 1, center aligned PWM

PB01 XPWM Channel 0/1 Burst Mode Control Bit

0: Channels 0 and 1 work independently in respective standard mode

1: Outputs of channels 0 and 1 are ANDed to XPWM0 in burst mode

PSx XPWM Channel x Single Shot Mode Control Bit

0: Channel x works in respective standard mode

1: Channel x operates in single shot mode

ST10F280 Datasheet(PDF) 90 Page - STMicroelectronics

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