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ST10F280 Datasheet(PDF) 11 Page - STMicroelectronics

Part # ST10F280
Description  16-bit MCU with MAC unit, 512 Kbyte Flash memory and 18 Kbyte RAM
PDF  239 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F280 Datasheet(HTML) 11 Page - STMicroelectronics

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ST10F280
List of figures
Doc ID 8673 Rev. 3
11/239
Figure 49.
Port 8 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 50.
Block diagram of Port 8 pins P8.7...P8.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 51.
PORT10 I/O and alternate functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 52.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 53.
XTIMER block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 54.
XADCINJ timer output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 55.
External connection for ADC channel injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 56.
Asynchronous mode of serial channel ASC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 57.
Synchronous mode of serial channel ASC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 58.
Synchronous serial channel SSC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 59.
Single CAN bus multiple interfaces - multiple transceivers. . . . . . . . . . . . . . . . . . . . . . . 156
Figure 60.
Single CAN bus dual interfaces - single transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 61.
Connection to two different CAN buses (e.g. for gateway application). . . . . . . . . . . . . . . 157
Figure 62.
CAN module address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 63.
Bit timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 64.
Message object address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 65.
Asynchronous reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 66.
Synchronous warm reset (short low pulse on RSTIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 67.
Synchronous warm reset (long low pulse on RSTIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 68.
Internal (simplified) reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 69.
Minimum external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 70.
External reset hardware circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 71.
External RC circuit on RPD pin for exiting power down mode with external interrupt . . . 183
Figure 72.
Simplified power down exit circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 73.
Power down exit sequence when using an external interrupt (PLL x 2) . . . . . . . . . . . . . . 184
Figure 74.
Supply / idle current as a function of operating frequency . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 75.
Input / output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 76.
Float waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 77.
Generation mechanisms for the CPU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 78.
Approximated maximum PLL Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 79.
External clock drive XTAL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 80.
External memory cycle: multiplexed bus, with / without read / write delay, normal ALE. . 218
Figure 81.
External memory cycle: multiplexed bus, with / without read / write delay, extended ALE219
Figure 82.
External memory cycle: multiplexed bus, with / without read / write delay, normal ALE,
read / write chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 83.
External memory cycle: multiplexed bus, with / without read / write delay, extended ALE,
read / write chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 84.
External memory cycle: demultiplexed bus, with / without read / write delay, normal ALE224
Figure 85.
External memory cycle: demultiplexed bus, with / without read / write delay, extended ALE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 86.
External memory cycle: demultiplexed bus, with / without read / write delay, normal ALE,
read / write chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 87.
External memory cycle: demultiplexed bus, no read / write delay, extended ALE, read /write
chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 88.
CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Figure 89.
External bus arbitration, releasing the bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 90.
External bus arbitration, (regaining the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 91.
SSC master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Figure 92.
SSC slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 93.
Package outline PBGA 208 (23 x 23 x 1.96 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235



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