MM32F103CET datasheet(16/89 Pages) MINDMOTION

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DS_MM32F103xx_o_Ver1.13

Specification

feature is 4 independent channels each for input capture/output compare, PWM or one-

pulse mode output.

The timer can work together or with the TIM1 advanced-control timer via the Timer Link

feature for synchronization or event chaining. Their counter can be frozen in debug mode.

Any of the general-purpose timers can be used to generate PWM outputs. They all have

independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the

digital outputs from 1 to 3 hall-effect sensors.

Basic timer

TIM16/TIM17

Every timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. They each

have a single channel for input capture/output compare, PWM or one-pulse mode output.

TIM16 and TIM17 have a complementary output with dead-time generation and indepen-

dent DMA request generation. Their counters can be frozen in debug mode.

Independent watchdog (IWDG)

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with

user-defined refresh window. It is clocked from an independent 40 KHz internal oscillator

and as it operates independently from the main clock, it can operate in Stop and Standby

modes. It can be used either as a watchdog to reset the device when a problem occurs,

or as a free running timer for application timeout management. It is hardware or software

configurable through the option bytes. The counter can be frozen in debug mode.

System window watchdog (WWDG)

The system window watchdog is based on a 7-bit downcounter that can be set as free

running. It can be used as a watchdog to reset the device when a problem occurs. It is

clocked from the APB clock (PCLK). It has an early warning interrupt capability and the

counter can be frozen in debug mode.

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a stan-

dard down counter. It features:

• A 24-bit down counter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0

• Programmable clock source

2.2.17 Universal asynchronous receiver/transmitter (UART)

UART provides hardware management of the CTS, RTS.

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