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MM32F103CET Datasheet(PDF) 10 Page - MindMotion Microelectronics |
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MM32F103CET Datasheet(HTML) 10 Page - MindMotion Microelectronics |
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10 / 89 page ![]() DS_MM32F103xx_o_Ver1.13 Specification 2.2.1 ARM® CortexTM-M3 and SRAM The ARM® CortexTM-M3 is a generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementa- tion, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM® CortexTM-M3 processors feature exceptional code-efficiency, delivering the high performance expected from an ARM core, with memory sizes usually associated with 8- and 16-bit devices. The devices have embedded ARM core and are compatible with all ARM tools and soft- ware. 2.2.2 Memory 512K Bytes of embedded Flash memory. 2.2.3 SRAM 128K Bytes of embedded SRAM. 2.2.4 Clocks and startup When the system is powered up, the default clock is from PLL with the resource from HSE 48 MHz oscillator. An external 2 ∼ 24 MHz clockcan also be configured to monitor the system during power up phases. If the system fails at power up, then the device will switch back to HSI clock directly. At the same time, a software interrupt can also be generated if it is enabled. Several prescalers allow the application to configure the frequency of the AHB and the APB domains. The maximum frequency of the AHB and the APB domains is 168MHZz.Refer to figure 3 for the clock drive block diagram. www.mm32mcu.com 4/83 |
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