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MM32F103CET Datasheet(PDF) 60 Page - MindMotion Microelectronics |
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MM32F103CET Datasheet(HTML) 60 Page - MindMotion Microelectronics |
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60 / 89 page ![]() DS_MM32F103xx_o_Ver1.13 Electrical characteristics Symbol Parameter Conditions Min Typ Max Unit CIO I/O pin capacitance 5 pF 1. Schmitt Trigger switching hysteresis voltage level.Data based on design simulation only. Not tested in production. 2. The leakage could be higher than the maximum value, if negative current is injected on adjacent pins. 3. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (10% order). All I/Os are CMOS (no software configuration required). Their characteristics cover more than the strict CMOS-technology. • For VIH: – If VDD is between [2.50V ∼ 3.08V]; use CMOS features. – If VDD is between [3.08V ∼ 3.60V]; include CMOS. • For VIL: – Use CMOS features. Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±20mA. n the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in 5.2: • The sum of the currents obtained from VDD for all I/O ports, plus the maximum operating current that the MCU obtains on VDD, cannot exceed the absolute maximum rating IVDD. • The sum of the currents drawn by all I/O ports and flowing out of VSS, plus the maximum operating current of the MCU flowing out on VSS, cannot exceed the absolute maximum rating IVSS. Output voltage levels Unless otherwise stated, the parameters listed in the table below are measured using the ambient temperature and VDD supply voltage in accordance with the condition Table 7. All I/O ports are CMOS compatible. Table 31. Output voltage characteristics Symbol Parameter Conditions Min Max Unit VOL ( 1) Output low level voltage for an I/O pin,when 8 pins absorb current CMOS Port,IIO = +8mA 2.7V < VDD < 3.6V 0.4 www.mm32mcu.com 54/83 |
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