STWBC2-HP datasheet(51/96 Pages) STMICROELECTRONICS

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Table 36. Buck switch configuration overview

Switch Buck side (before inductor)

Switch configuration

LSB_ACTIVE

Comment

Low-side switch is diode

Low-side switch is MOSFET

When the BB-DCDC is running a buck/boost hardware with passive switches on low-side buck and high-side

boost, a single gate driver can drive the two remaining active switches. This means that HSB+LSA have to drive

the gate driver.

However, coherent pairs of BB-DCDC controller signals are routed to the gate driver, so HSB+LSB and

HSA+LSA. To obtain HSB+LSA in the gate driver, it is possible to swap LSA and LSB at the output of the

BB-DCDC controller. Set the bit SWAP_LSA_LSB of the DCDC_CTRL register to enable the LSA/LSB swapping.

Depending on the application, it is possible to disable some protection functions in the DCDC_CTRL register:

•

Set DISABLE_OVER_CURRENT to disable the overcurrent limiter function

•

Set DISABLE_VIN_DROP to disable the VIN drop limiter function

•

Set DISABLE_OVERLOAD to disable the overload detection function

The STARTUP_RATE field in the DCDC_STARTUP_BLANK_TIME register allows adjusting the smoothing of

start-up current. Set this field to the slowest start-up time if possible.

The BB-DCDC supports on-the-fly changes of target voltage. In case of large increase of target voltage, the

BB-DCDC can create large input current spikes to reach the required voltage as fast as possible. Automatic

voltage ramp can be enabled to reduce such current spikes. To do so, set the bit PROGRESSIVE_V_DAC in the

DCDC_CTRL register.

The BB-DCDC must probe the switching node it is driving. BB-DCDC uses V1 comparator to monitor the buck

side (if any) and V2 comparator to monitor the boost side (if any). Different pins of the STWBC2-HP can be

assigned to V1 and V2 comparator. Use the V1_MUX and V2_MUX fields of the DCDC_COMPARATOR_MUX

gate drivers or GD_IO3 pin).

The BB-DCDC manages fixed deadtime between high-side and low-side drive. Adjust the

DCDC_GD_DEAD_TIME register to set the deadtime required by the gate drivers.

The start of charge step of BB-DCDC can be synchronized with a self-generated clock. Adjust the

DCDC_SYNC_PERIOD register to set the period of this clock in counts of BB-DCDC clock period. A value of

0 disables the synchronization. The synchronization clock can be changed during the BB-DCDC operation.

When the new value is written, set the bit UPDATE of the DCDC_CTRL register and the BB-DCDC takes it into

account.

The default timing values of the BB-DCDC controller are valid for inductance in the range of 2 µH to 10 µH. It is

recommended to keep these default values in the registers

(DCDC_PRECHARGE_TIME_SHORT, DCDC_PRECHARGE_TIME_LONG,

DCDC_PRESDISCHARGE_TIME_SHORT, DCDC_PRESDISCHARGE_TIME_LONG, DCDC_PROBE_TIME,

DCDC_RELAX_TIME_L, DCDC_RELAX_TIME_H, DCDC_GD_TIME_BEFORE_REFRESH,

DCDC_GD_REFRESH_TIME, DCDC_OVERCURRENT_RATE, DCDC_OVERCURRENT_LOCK_TIME,

DCDC_OVERLOAD_THR).

The output voltage range of the BB-DCDC has to be configured according to the range of the application. Set the

range in the DCDC_DAC_RANGE register.

When the configuration above is done, the DC-DC can be enabled or disabled and the voltage can be changed

on-the-fly.

To enable the BB_DCDC set the bit ENABLE in the DCDC_CTRL register. Clear this bit to disable the BB_DCDC.

To change the voltage target, set the corresponding code to the registers DCDC_DAC_VALUE_L &

DCDC_DAC_VALUE_H. The written value is taken into account only when the self-clearing bit UPDATE_V_DAC

of register DCDC_DAC_VALUE_H is set. It is then recommended to write the L register first and when writing the

H register, OR the value with 0x80. This procedure combines the H value write with the update request.

STWBC2-HP

Digital AFE functions

DS13825 - Rev 1.0

page 51/96

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