STWBC2-HP datasheet(67/96 Pages) STMICROELECTRONICS

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The addr vector is asynchronously provided to the peripheral bus based on the spi_clk. The peripheral bus read

operation being completely combinational, there is no synchronization between clk and spi_clk domain.

The clk domain receives access request from the spi_clk domain through read and write toggling flags. These

flags are synchronized on clk domain with dual edge. Since a flag is seen toggled, the clk domain generates the

corresponding re or we pulse. The addr and wdata vectors are guaranteed to be static before and during the re or

we pulse generated on clk domain.

Here below is shown the SPI basic timing diagram.

Figure 66. MCU-SPI interface timing diagram overview

The next section details all the supported transaction operations.

2.2.13.3.1

Single byte write access:

The first byte transmitted by the master after NSS goes low corresponds to the access address. The MSB of this

byte is 0, meaning that it is a write access. During the transmission of the first byte, the slave transmits 8bits data

at 0.

The second byte sent by the master is the 8bits data to be written at the requested address. While the data

byte to be written is sent by the master, the slave transmits the value at address+1. This offers the possibility to

combine a write and read on adjacent address.

The write process stops when NSS comes high.

Figure 67. Single byte write access

2.2.13.3.2

Single byte read access:

The first byte transmitted by the master after NSS goes low corresponds to the access address. The MSB of this

byte is 1 meaning that it is a read access. During the transmission of the first byte, the slave transmits 8bits data

at 0.

The second byte sent by the master is not used and must be 0. During the master transmission of second byte,

the slave transmits the value at address.

The read process stops when NSS comes high.

STWBC2-HP

Digital AFE functions

DS13825 - Rev 1.0

page 67/96

STWBC2-HP Datasheet(PDF) 67 Page - STMicroelectronics