STWBC2-HP datasheet(61/96 Pages) STMICROELECTRONICS

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•

Select the NVM memory access request by setting the NVM_HW_REQ wc-bit field of register

NVM_CTRL_0.

•

Wait for the command completion notified by the NVM_EOC. In case of abort notified by NVM_ABRT bit field

(this event should be avoided thanks to the SW interlock procedures described in the first step) the entire

command sequence has to be reiterated.

•

Reset the NVM status bit by setting the NVM_STS_CLR wc bit field of register NVM_CTRL_0.

2.2.11.5

Operating parameters

Table 45 summarizes the IP functional operating parameters.

Table 45. NVM operating parameters

Parameter

Value

NVM operating clock

4 MHz to 5 MHz

2.2.11.6

Configuration register overview

Table 46 shows the list of NVM configuration registers overview

Table 46. NVM configuration registers overview

Registers overview

Name

Description

Type

Page

Offset

Reset val.

NVM_CTRL_0

NVM control configuration 0

R/W

0x02

0x00

NVM_CTRL_1

NVM control configuration 1

R/W

0x03

0x00

NVM_CTRL_2

NVM control configuration 2

R/W

0x04

0xC2

NVM_DATA_0

NVM data register

R/W

0x05

0xYY(1)

NVM_DATA_1

NVM data register

R/W

0x06

0xYY(1)

NVM_DATA_2

NVM data register

R/W

0x07

0xYY(1)

NVM_DATA_3

NVM data register

R/W

0x08

0xYY(1)

NVM_DATA_4

NVM data register

R/W

0x09

0xYY(1)

NVM_DATA_5

NVM data register

R/W

0x0A

0xYY(1)

NVM_DATA_6

NVM data register

R/W

0x0B

0xYY(1)

NVM_DATA_7

NVM data register

R/W

0x0C

0xYY(1)

1. Sector-0 byte values in functional mode or 0x00 in test mode.

2.2.12

RCC (Reset & Clock Controller) circuit

2.2.12.1

Overview

This block controls the generation of the Reset and Clock signals after the IC power-up. Whenever the power is

applied to the system, this block grants the congruent sequence of internal reset controls and the delivery of the

system clock.

2.2.12.2

Feature list

•

Two independent clock and reset line domains

•

Global reset assertion on HW/SW reset commands

•

Selective IP SW reset generation

•

PLL clock control circuit

•

Control clock gating for every digital IP

•

DMD configurable clock line.

STWBC2-HP

Digital AFE functions

DS13825 - Rev 1.0

page 61/96

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