STWBC2-HP datasheet(54/96 Pages) STMICROELECTRONICS

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After power-up all the interrupt request lines are masked; these may be enabled by configuring the INT_EN_<x>

registers. When the interrupt rising edge is detected the “IRQ” interrupt request signal is asserted.

The interrupt source request is memorized and stored in the readable register INT_STATUS_<x> then the

interrupt notify is clearable by setting to “1” the corresponding INT_CLEAR_<x> bit. The interrupt row request

lines may be read from the INT_SOURCE_<x> registers.

Note that enabling of a line for which the source is already 1 has no effect.

The status signal of each line is ORed together to generate the IRQ signal going to MCU. The source, enable,

clear and status vectors are mapped to SPI registers. Some interrupt source signals are externally synchronized.

2.2.9.3.1

Interrupt level or pulse generation

The interrupt controller can generate a pulse on IRQ output if pulse_duration is not 0. The pulse generation is

interesting to use if the microcontroller that receives the IRQ line is edge sensitive only and cannot be configured

in level.

When the controller is configured to generate pulse, the IRQ line is forced to 0 for pulse_duration cycle count

when any interrupt is cleared. By consequence, if another interrupt was pending, after being forced to 0, the IRQ

line returns to 1 and is representing an edge that can be captured by the microcontroller.

2.2.9.3.2

Interrupt table

Table 39 shows the Interrupt request assignment:

Table 39. ITC Interrupt table overview

Interrupt Table

Irq#

Request line

Description

io0_incoherent

IO0 drive incoherence fault

io1_incoherent

IO1 drive incoherence fault

Io2_incoherent

IO2 drive incoherence fault

Io3_incoherent

IO3 drive incoherence fault

gdls0_incoherent

gdls0 drive incoherence fault

gdls1_incoherent

gdls1 drive incoherence fault

gdls2_incoherent

gdls2 drive incoherence fault

pll_unlock

PLL lose lock

dcdc_error

DCDC error fault

dcdc_vin_drop

DCDC voltage drop fault

dcdc_over_current

DCDC overcurrent fault

11-17

RFU

Reserved for future use

pwm_status_fsk_fifo_half_full

PWM FSK FIFO count is passing below half capacity (time to refill)

pwm_status_fsk_fifo_empty

PWM FSK FIFO is empty (end of FSK data)

Note:

All interrupt request signals are active high.

STWBC2-HP

Digital AFE functions

DS13825 - Rev 1.0

page 54/96

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