STWBC2-HP datasheet(26/96 Pages) STMICROELECTRONICS

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Figure 29. HR-PWM subsystem overview

The Main PWM runs with high resolution timings. To do so, the clocking of the cell is made through 17 phases of

a 40 MHz typical clock. This provides a resolution equivalent to a clock at 680 MHz.

2.2.1.3.1

Sequencer PWM signal generation

The signal generation block is designed around a controller that processes the event list. Each event in the list is

informing about a delay before applying a specific toggling of the PWM outputs. The delay is made of a coarse

value corresponding to a count of clock cycles and a fine value corresponding to a count of clock phases.

When the delay expires, the controller applies the required toggling on PWM outputs and selects the clock phase

in order to achieve the next fine delay. The controller treats then the next active event in the list. When the

controller reaches the end of the event list, it restarts processing the list from the beginning.

Figure 30 shows the sequences controlled by the scheduler logic.

Figure 30. Sequencer circuit overview

2.2.1.3.2

FSK modulation

Each event in the list can be tagged to be active only with a specific state of FSK bit, either 0 or 1. With such

tagging, some events in the list become conditionals so the PWM generation depends on the state of the FSK bit.

This feature allows programming the signal generation block to generate frequency shift keying messaging.

The FSK bit generation is using a FIFO:

STWBC2-HP

Digital AFE functions

DS13825 - Rev 1.0

page 26/96

STWBC2-HP Datasheet(PDF) 26 Page - STMicroelectronics