STWBC2-HP datasheet(35/96 Pages) STMICROELECTRONICS

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Table 24. Phase demodulator operating parameters

Parameter

Condition

Value

Operating frequency

8 MHz to 16 MHz

Chronometer data rate

100 – 300 ks/s

Target sampling rate

40 ks/s

LPF frequencies

Fs=40 ks/s

4 kHz, 8 kHz, 12 kHz, 16 kHz

HPF frequencies

Fs=40 ks/s

200 Hz, 300 Hz, 500 Hz, 650 Hz

Input data width

17 bits

Output data width

1 bit

2.2.2.6

Configuration register overview

Table 25. Phase demodulator configuration registers overview

Registers overview

Name

Description

Type

Page Offset

Reset val.

P_DEMOD

Phase demodulation configuration

R/W

0x1E

0x01

P_DEMOD_CLK_L

Phase demodulation clock configuration

R/W

0x1F

0x00

P_DEMOD_CLK_H

Phase demodulation clock configuration

R/W

0x20

0x00

P_DEMOD_HYSTERESIS Phase demodulation hysteresis configuration

R/W

0x21

0x00

2.2.3

QF controller

2.2.3.1

Overview

This block is used to control the analog driver which stimulates the LC resonant network keeping its natural

oscillation at steady-state. Changes in the Q factor allows the system to detect foreign object presence and to

check for an in-range receiver periodically (according to the Qi standard) and with minimum SW intervention.

2.2.3.2

Feature list

•

Blank time to get noise and disturbances immunity (frequency high limit)

•

Input capture of waveform zero-cross for oscillation period measurement

•

Synchronous FSM controlling an asynchronous loop for optimal capture resolution

•

Time-out function to set the frequency low limit

2.2.3.3

Functional description

The QF measurement system uses an analog driver providing a symmetrical square wave current of

programmable strength. The system uses the IV-converter zero-voltage cross detector attached to the ringing

node. The zc_det signal is the output of this detector and is asynchronously fed back to the current generator as

source/sink command (QF_drv). A counter in the digital machine is dedicated to capturing the oscillation period

and to providing blanking and time-out function. The polarity of the output driver (QF_drv) may be inverted by the

POLARITY field of the QF_CTRL control register.

Here below is shown the circuit block diagram.

STWBC2-HP

Digital AFE functions

DS13825 - Rev 1.0

page 35/96

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