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STWBC2-HP Datasheet(PDF) 55 Page - STMicroelectronics |
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STWBC2-HP Datasheet(HTML) 55 Page - STMicroelectronics |
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55 / 96 page  2.2.9.4 Programming To prevent interrupt missing, the following sequence should be applied during the interrupt controller configuration: 1. Configure INT_PULSE_DURATION to generate pulse on the IRQ line (0 means no pulse). 2. Enable all the interrupt source lines needed to be monitored through the registers INT_EN_<x>. 3. When a source edge happens, the IRQ signal generates an interrupt on the MCU companion DIE. 4. While the IRQ signal is 1, the MCU enters into its interrupt handler. The handler routine (ISR) should perform the following actions: a. Get interrupt status by reading INT_STATUS_<x> registers. b. Check the status lines at 1 by priority order and decide to treat a first one. c. Before treating the chosen, the interrupt, clear it by writing 1 to the corresponding bit in INT_CLEAR_<x> register. d. Manage the interrupt and reach the end of interrupt handler (don’t loop on the status). e. The clearing of the chosen line might release the IRQ line. It is the case if this line was the only one active. In this situation, the interrupt handler exits. If another interrupt were present or if the same interrupt fires again, the IRQ line is 1 at the end of interrupt handler. So, since the handler exits, the MCU re-enters it immediately and the same sequence is processed again (this creates indirectly a loop). To simplify the SW interrupt handling routine, the fault interrupts are mapped on the lower interrupt request lines. 2.2.9.5 Configuration register overview Table 40 shows the list of ITC configuration registers overview Table 40. ITC configuration registers overview Registers overview Name Description Type Page Offset Reset val. INT_EN_0 Interrupt enabling R/W 0 0x40 0x00 INT_EN_1 Interrupt enabling R/W 0 0x41 0x00 INT_EN_2 Interrupt enabling R/W 0 0x42 0x00 INT_CLEAR_0 Interrupt clear Wsc 0 0x43 0x00 INT_CLEAR_1 Interrupt clear Wsc 0 0x44 0x00 INT_CLEAR_2 Interrupt clear Wsc 0 0x45 0x00 INT_STATUS_0 Interrupt status R 0 0x46 0x00 INT_STATUS_1 Interrupt status R 0 0x47 0x00 INT_STATUS_2 Interrupt status R 0 0x48 0x00 INT_SOURCE_0 Interrupt source status R 0 0x49 0xYY(1) INT_SOURCE_1 Interrupt source status R 0 0x4A 0xYY(1) INT_SOURCE_2 Interrupt source status R 0 0x4B 0xYY(1) INT_PULSE Interrupt pulse configuration R/W 0 0x4C 0x00 1. Refer to register definition. 2.2.10 Protection 2.2.10.1 Overview This block is responsible of the fault error detection inside the Analog Front-End (AFE) logic which is notified to the FW application running on the MCU companion DIE. STWBC2-HP Digital AFE functions DS13825 - Rev 1.0 page 55/96 |
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