STM32WBA50KG datasheet(44/110 Pages) STMICROELECTRONICS

44 / 110 page

Functional overview

STM32WBA50KG

44/110

DS14688 Rev 1

3.25

Tamper and backup registers (TAMP)

The anti-tamper detection circuit is used to protect sensitive data from external attacks. 32

32-bit backup registers are retained in all low-power modes. The backup registers, as well

as other secrets in the device, are protected by this anti-tamper detection circuit with

tamper pins and nine internal tampers. The external tamper pins can be configured for level

detection with or without filtering, or active tamper that increases the security level by auto

checking that the tamper pins are not externally opened or shorted.

TAMP main features:

•

A tamper detection can erase the backup registers, SRAM2, ICACHE and

cryptographic peripherals.

•

32 32-bit backup registers:

–

The backup registers (TAMP_BKPxR) are implemented in the Backup domain that

remains powered-on by VDD power.

•

Up to three tamper pins for external tamper detection events:

–

Active tamper mode: continuous comparison between tamper output and input to

protect from physical open-short attacks

–

Flexible active tamper I/O management: from one (input associated to its own

exclusive output) to two meshes (single output shared for up to two tamper inputs)

–

Passive tampers: ultra-low power edge or level detection with internal pull-up

hardware management

–

Configurable digital filter

•

Nine internal tamper events to protect against transient or environmental perturbation

attacks:

–

LSE monitoring

–

RTC calendar overflow

–

JTAG/SWD access if RDP different from 0

–

Monotonic counter overflow

–

Cryptographic peripherals fault (RNG, AES, PKA)

–

Independent watchdog reset when tamper flag is already set

–

Three ADC4 watchdogs

•

Each tamper can be configured in two modes:

–

Hardware mode: immediate erase of secrets on tamper detection, including

backup registers erase

–

Software mode: erase of secrets following a tamper detection launched by

software

•

Any tamper detection can generate an RTC time stamp event.

•

Monotonic counter

3.26

Inter-integrated circuit interface (I2C)

The device embeds one I2C, refer to Table 15 for the features implementation.

The I2C bus interface handles communications between the microcontroller and the serial

I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.

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