STM32WBA50KG datasheet(91/110 Pages) STMICROELECTRONICS

91 / 110 page

DS14688 Rev 1

91/110

STM32WBA50KG

Electrical characteristics

103

CADC

Internal sample and

hold capacitor

tADCVREG_STUP

ADC voltage regulator

startup time

µs

tSTAB

ADC power-up time

(3 x 1/fADC) + 1 conversion

cycle

tOFF_CAL

Offset calibration time

1/fADC

tLATR

Trigger conversion

latency

WAIT = 0, AUTOFF = 0,

DPD = 0, fADC = HCLK

WAIT = 0, AUTOFF = 1,

DPD = 0, fADC = HCLK/2

WAIT = 0, AUTOFF = 1,

DPD = 1, fADC = HCLK/4

3.75

Sampling time

1.5

814.5

tCONV

Total conversion time

(including sampling

time)

Resolution = N bits,

VREFPROTEN = 0

ts + N + 0.5

Resolution = N bits,

VREFPROTEN = 1,

VREFSECSMP = 0

ts + N +

0.5

ts + N +

1.5

Resolution = N bits,

VREFPROTEN = 1,

VREFSECSMP = 1

ts + N +

0.5

ts + N +

2.5

IDDA(ADC)

ADC consumption

on VDDA

fs = 2.5 Msps

378

µA

fs = 1 Msps

190

fs = 10 ksps

AUTOFF = 1, DPD = 0,

no conversion

-9-

AUTOFF = 1, DPD = 1,

no conversion

-0.11-

1. Specified by design, not tested in production.

2. The voltage booster on the ADC switches must be used when VDDA < 2.4 V (embedded I/O switches).

VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.

4. The tolerance is two LSBs.

Table 68. 12-bit ADC4 characteristics (1) (2) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 69. Maximum RAIN for 12-bit ADC4(1) (2) (3)

Resolution

RAIN (Ω)

Sampling time (ns)

Sampling cycles at 35 MHz

Sampling cycles at 55 MHz

12 bits

276

12.5

19.5

288

100

306

150

336

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