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STM32WBA50KG Datasheet(PDF) 42 Page - STMicroelectronics |
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STM32WBA50KG Datasheet(HTML) 42 Page - STMicroelectronics |
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42 / 110 page  Functional overview STM32WBA50KG 42/110 DS14688 Rev 1 • 16-bit up counter with 16-bit autoreload register • 3-bit prescaler with following possible dividing factors (1, 2, 4, 8, 16, 32, 64, 128) • Selectable clock – Internal clock sources: LSE, LSI, HSI16 or APB clock – External clock source over LPTIM input (working with no LP oscillator running, used by Pulse Counter application) • 16-bit ARR autoreload register • 16-bit capture/compare register • Continuous/One-shot mode • Selectable software/hardware input trigger • Programmable digital glitch filter • Configurable output: pulse, PWM • Configurable I/O polarity • Encoder mode • Repetition counter • Up to two independent channels for: – Input capture – PWM generation (edge-aligned mode) – One-pulse mode output • Interrupt generation on ten events • DMA request generation on the following events: – Update event – Input capture 3.23.4 Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and a 10-bit prescaler. It is clocked from the independent LSI and, as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software enabled through the option bytes. The counter can be frozen in low-power and Debug mode. 3.23.5 Window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in Debug mode. |
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