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STM32WBA50KG Datasheet(PDF) 1 Page - STMicroelectronics

Part # STM32WBA50KG
Description  Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M33 with FPU, Bluetooth® 5.4 radio solution
PDF  110 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32WBA50KG Datasheet(HTML) 1 Page - STMicroelectronics

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September 2024
DS14688 Rev 1
1/110
STM32WBA50KG
Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M33
with FPU, Bluetooth® 5.4 radio solution
Datasheet
- production data
Features
• Includes ST state-of-the-art patented
technology
• Ultra-low power radio
– 2.4 GHz radio
– RF transceiver supporting Bluetooth® Low
Energy specification 5.4
– RX sensitivity: -96 dBm (Bluetooth® Low
Energy at 1 Mbps)
– Programmable output power, +4 dBm with
1 dB steps
– Integrated balun to reduce BOM
– Single crystal operation
– Suitable for systems requiring compliance
with radio frequency regulations ETSI EN
300 328, EN 300 440, FCC CFR47 Part 15
and ARIB STD-T66
• Operating conditions:
– 1.71 to 3.6 V power supply
– -40 to 85 °C temperature range
• Ultra-low power platform with
FlexPowerControl
– Autonomous peripherals with DMA,
functional down to Stop 1 mode
– 160 nA Standby mode (8 wake-up pins)
– 2.25 µA Standby mode with 16-Kbyte
SRAM
– 20.2 µA Stop mode with 16-Kbyte SRAM
– 41.8 µA/MHz Run mode at 3.3 V
– Radio: Rx 7.91 mA / Tx at 0 dBm 10.51 mA
– Embedded regulator LDO
• Core: Arm® 32-bit Cortex®-M33 CPU with
MPU, DSP, and FPU
• ART Accelerator: 8-Kbyte instruction cache
allowing 0-wait-state execution from flash
memory (frequency up to 100 MHz,
150 DMIPS)
• Benchmarks
– 1.5 DMIPS/MHz (Drystone 2.1)
– 410 CoreMark® (4.10 CoreMark/MHz)
• Real time clock (RTC) with hardware calendar,
alarms, and calibration
• Clock sources
– 32 MHz crystal oscillator
– 32 kHz crystal oscillator (LSE)
– Internal low-power 32 kHz (±5%) RC
– Internal 16 MHz factory trimmed RC (±1%)
– PLL for system clock and ADC
• Memories
– 1 Mbyte flash memory with ECC, including
256 Kbytes with 100k cycles
– 64-Kbyte SRAM, including 48 KB with
parity check
– 512-byte (32 rows) OTP
• Rich analog peripherals (independent supply)
– 12-bit ADC 2.5 Msps, with hardware
oversampling
• Communication peripherals
– Two UARTs (ISO 7816, IrDA, modem)
– SPI
– I2C Fm+ (1 Mbit/s), SMBus/PMBus®
UFQFPN32 (5 x 5 mm)
www.st.com


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