STM32WBA50KG datasheet(100/110 Pages) STMICROELECTRONICS

100 / 110 page

Electrical characteristics

STM32WBA50KG

100/110

DS14688 Rev 1

Table 78. SPI characteristics(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fSCK

1/tSCK

Clock frequency

Master receiver mode

2.7 V ≤ VDD ≤ 3.6 V

MHz

Master receiver mode

1.71 V ≤ VDD < 2.7 V

Master transmitter mode

2.7 V ≤ VDD < 3.6 V

Master transmitter mode

1.71 V ≤ VDD < 2.7 V

Slave receiver mode

1.71 V ≤ VDD ≤ 3.6 V

100

Slave transmitter mode

2.7 V ≤ VDD ≤ 3.6 V, voltage range 1

35.5(2)

Slave transmitter mode

1.71 V ≤ VDD < 2.7 V, voltage range 1

24(2)

Slave transmitter mode

2.7 V ≤ VDD ≤ 3.6 V, voltage range 2

tsu(NSS) NSS setup time

Slave mode

4*Tpclk

th(NSS) NSS hold time

Slave mode

2*Tpclk

tw(SCKH)

tw(SCKL)

SCK high and low time

Master mode(3)

tSCK/2 - 1 tSCK/2 tSCK/2 + 1

tsu(MI)

Data input setup time

Master mode

4.5

tsu(SI)

Slave mode

2.5

th(MI)

Data input hold time

Master mode

2.0

th(SI)

Slave mode

1.0

ta(SO)

Data output access time

Slave mode

10.5

21.0

tdis(SO) Data output disable time

10.5

13.0

21.0

tv(SO)

Data output valid time

Slave mode (after enable edge)

2.7 V ≤ VDD ≤ 3.6 V, voltage range 1

10.5

14.0

Slave mode (after enable edge)

1.71 V ≤ VDD < 2.7 V, voltage range 1

16.5

20.5

Slave mode (after enable edge)

2.7 V ≤ VDD ≤ 3.6 V, voltage range 2

14.0

18.5

Slave mode (after enable edge)

1.71 V ≤ VDD < 2.7 V, voltage range 2

21.0

25.5

tv(MO)

Master mode

0.5

2.0

th(SO)

Data output hold time

Slave mode

7.5

th(MO)

Master mode

1. Evaluated by characterization, not tested in production.

2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI), which must fit into SCK low or

high phase preceding the SCK sampling edge. This value can be achieved when SPI communicates with a master having

tsu(MI) = 0 while Duty(SCK) = 50%.

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