STM32WBA50KG datasheet(98/110 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32WBA50KG

98/110

DS14688 Rev 1

5.3.26

USART characteristics

Unless otherwise specified, the parameters given in Table 77 are derived under the ambient

temperature, fPCLKx frequency and supply voltage conditions summarized in Table 26, with

the following configuration:

•

Output speed set to OSPEEDRy[1:0] = 10

•

Capacitive load CL = 30pF

•

Measurement points are done at 0.5 x VDD

•

I/O compensation cell activated

•

Voltage scaling range 1

Refer to Section 5.3.16 for more details on the I/O input/output characteristics (NSS, CK,

TX, RX for USART).

Table 77. USART characteristics(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fCK

USART clock

frequency

Master mode, 1.71 V ≤ VDD ≤ 3.6 V

12.5

MHz

Slave receiver, 1.71 V ≤ VDD ≤ 3.6 V

33.0

Slave transmitter, 2.7 V ≤ VDD ≤ 3.6 V

35.5

Slave transmitter, 1.71 V ≤ VDD < 2.7 V

25.0

tsu(NSS)

NSS setup

time

Slave mode(2)

tker + 2

th(NSS)

NSS hold

time

Slave mode

tw(CKH)

tw(CKL)

SCK high

and low time

Master mode

(1 / fCK) / 2

- 1

(1 / fCK) / 2

+ 1

tsu(RX)

Data input

setup time

Master mode

18.5

Slave mode

1.5

th(RX)

Data input

hold time

Master mode

0.5

Slave mode

tv(TX)

Data output

valid time

Slave mode, 2.7 V ≤ VDD ≤ 3.6 V

Slave mode, 1.71 V ≤ VDD < 2.7 V

Master mode

0.5

1.0

th(TX)

Data output

hold time

Slave mode

Master mode

1. Evaluated by characterization, not tested in production, unless otherwise specified.

2. Tker is the usart_ker_ck_pres clock period.

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