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STM32WBA50KG Datasheet(PDF) 20 Page - STMicroelectronics |
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STM32WBA50KG Datasheet(HTML) 20 Page - STMicroelectronics |
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20 / 110 page ![]() Functional overview STM32WBA50KG 20/110 DS14688 Rev 1 During power-up and power-down phases, respect the following requirements: • When VDD is below 1 V, other power supplies (namely VDDA) must remain below VDD + 300 mV. • When VDD is equal to or above 1 V, other power supplies are independent. • During the power-down phase, VDD can temporarily become lower than other supplies only if the energy provided to the MCU remains below 1 mJ. This allows external decoupling capacitors to be discharged with different time constants during the power-down transient phase. Figure 4. Power-up/down sequence 1. VDDX refers to power supply VDDA. 3.9.2 Power supply supervisor The devices have an integrated ultra-low power BOR (brownout reset) active in all modes. The BOR ensures proper operation after power-on and during power-down. The devices remain in reset mode when the monitored supply voltage VDD is below a specified threshold, without the need for an external reset circuit. The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected through option bytes.The devices feature an embedded PVD (programmable voltage detector) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below and/or rises above the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. The devices support dynamic voltage scaling to optimize its power consumption in Run mode. The voltage from the main regulator that supplies the logic (VCORE) can be adjusted according to the system’s maximum operating frequency. The main regulator operates in the following ranges: • Range 1 (VCORE = 1.2 V) with CPU and peripherals running at up to 100 MHz • Range 2 (VCORE = 0.9 V) with CPU and peripherals running at up to 16 MHz MSv47490V1 0.3 1 VBOR0 3.6 Operating mode Power-on Power-down time V VDDX (1) VDD Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD |
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