STM32WBA50KG datasheet(32/110 Pages) STMICROELECTRONICS

32 / 110 page

Functional overview

STM32WBA50KG

32/110

DS14688 Rev 1

•

Per channel event generation, on any of the following events: transfer complete or half

transfer complete or data transfer error or user setting error, and/or update linked-list

item error or completed suspension

•

Per channel interrupt generation, with separately programmed interrupt enable per

event

•

Eight concurrent DMA channels:

–

Per channel FIFO for queuing source and destination transfers

–

Intra-channel DMA transfers chaining via programmable linked-list into memory,

supporting two execution modes: run-to-completion and link step mode

–

Intra-channel and inter-channel DMA transfers chaining via programmable DMA

input triggers connection to DMA task completion events

•

Per linked-list item within a channel:

–

Separately programmed source and destination transfers

–

Programmable data handling between source and destination: byte-based

reordering, packing or unpacking, padding or truncation, sign extension and

left/right realignment

–

Programmable number of data bytes to be transferred from the source, defining

the block level

–

Linear source and destination addressing: either fixed or contiguously

incremented addressing, programmed at a block level, between successive single

transfers

–

Programmable DMA request and trigger selection

–

Programmable DMA half-transfer and transfer complete events generation

–

Pointer to the next linked-list item and its data structure in memory, with automatic

update of the DMA linked-list control registers

•

Debug:

–

Channel suspend and resume support

–

Channel status reporting including FIFO level and event flags

Table 8. GPDMA1 channels implementation and usage

Channel x

Hardware parameters

Features

dma_fifo_

size[x]

dma_

addressing[x]

x = 0 to 5

Channel x is implemented with:

– a FIFO of 8 bytes, 2 words

– fixed/contiguously incremented addressing

These channels may be also used for GPDMA transfers,

between an APB or AHB peripheral and SRAM.

x = 6 to 7

Channel x is implemented with:

– a FIFO of 32 bytes, 8 words

– fixed/contiguously incremented addressing

These channels may be also used for GPDMA transfers,

between a demanding AHB or APB peripheral and SRAM.

STM32WBA50KG Datasheet(PDF) 32 Page - STMicroelectronics

STM32WBA50KG Datasheet(HTML) 32 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL