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STM32WBA50KG Datasheet(PDF) 80 Page - STMicroelectronics

Part # STM32WBA50KG
Description  Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M33 with FPU, Bluetooth® 5.4 radio solution
PDF  110 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32WBA50KG Datasheet(HTML) 80 Page - STMicroelectronics

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Electrical characteristics
STM32WBA50KG
80/110
DS14688 Rev 1
Low-speed internal (LSI) RC oscillator
5.3.11
PLL characteristics
The parameters given in Table 54 are derived from tests performed at ambient temperature
and under the supply voltage conditions summarized in Table 26.
TRIM(2)
User trimming step
-
18
29
40
kHz
DuCyHSI16(2)
Duty cycle
-
45
-
55
%
tsu(HSI16)(2)
Startup time
-
-
2.5
3.6
μs
tstab(HSI16)(2)
Stabilization time
-
-
4
6
IDD(HSI16)(2)
Power consumption
-
-
150
210
μA
1. Evaluated by characterization, not tested in production, unless otherwise specified. It does not take into account package
and soldering effects.
2. Specified by design, not tested in production.
Table 52. HSI16 oscillator characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Table 53. LSI1 oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fLSI1
Frequency
VDD = 3.0 V, TJ = 30 °C, LSIPREDIV = 1
0.245 0.25 0.255
kHz
VDD = 3.0 V, TJ = 30 °C, LSIPREDIV = 0
31.4
32.0
32.6
1.71 V ≤ VDD ≤ 3.6 V, TJ = -40 to 85 °C,
LSIPREDIV = 0 (1)
30.4
32.0
33.6
DuCyLSI1
Duty cycle
LSIPREDIV = 1
-
50
-
%
tSU(LSI1)(2) Startup time
-
-
230
260
μs
tSTAB(LSI1)(2) Stabilization time 5% of final frequency
-
230
260
IDD(LSI1)(2)
Power
consumption
LSIPREDIV = 0
-
140
255
nA
LSIPREDIV = 1
-
130
240
1. Evaluated by characterization, not tested in production, unless otherwise specified.
2. Specified by design, not tested in production.
Table 54. PLL characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPLL_IN(1)
PLL input clock
-
4
-
16
MHz
DuCyPLL_IN(1) PLL input clock duty cycle
-
10
-
90
%
fPLL_OUT(1)
PLL output clock P, Q, and R
-
1
-
100
MHz
DuCyPLL_OUT(1) PLL output clock duty cycle
Division 1
40
-
60
%
fVCO_OUT(1)
PLL VCO output
-
128
-
544
MHz



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