STM32WBA50KG datasheet(28/110 Pages) STMICROELECTRONICS

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Functional overview

STM32WBA50KG

28/110

DS14688 Rev 1

3.9.3

Reset mode

To improve the consumption under reset, the I/Os state under and after reset is “analog

state” (the I/O Schmitt trigger is disabled). In addition, the internal reset pull-up is

deactivated when the reset source is internal.

3.10

Reset and clock controller (RCC)

The RCC (reset and clock controller) manages device and peripheral reset and distributes

the clocks coming from the different oscillators to the core and to the peripherals. It also

manages the clock gating for low-power modes and ensures the clock robustness. It

features:

•

Device reset source monitoring.

•

Individual peripheral reset control.

•

Clock prescaler: to get the best trade-off between speed and current consumption, the

clock frequency to the CPU and peripherals can be adjusted by a programmable

prescaler.

•

Clock selection system: clock sources can be changed safely on-the-fly in Run mode

through a configuration register.

•

Clock management: to reduce the power consumption, the clock controller can stop the

clock to the core, individual peripherals, or memory.

•

System clock source: different clock sources can be used to drive the system clock

SYSCLK:

–

HSE32 (32 MHz high-speed external crystal oscillator), trimmable by software.

The HSE32 can also be used with an external clock.

–

HSI16 (16 MHz high-speed internal RC oscillator), trimmable by software.

–

System PLL that can be fed by HSE32 or HSI16 with a maximum output frequency

at 100 MHz.

•

Auxiliary clock source: three ultra-low power clock sources that can be used to drive,

for instance, the real-time clock:

–

LSE (32.000 kHz or 32.768 kHz low-speed external crystal oscillator), supporting

programmable drive capability modes. The LSE can also be configured in bypass

mode for an external clock.

–

LSI (32 kHz low-speed internal RC oscillators), also used to drive the independent

watchdog. The LSI1 clock absolute accuracy is ±5%, it can be divided by 128 to

output a 250 Hz as source clock.

9. U(S)ART and LPUART reception and transmission are functional and autonomous in Stop mode in asynchronous and in

SPI master modes, and generate a wake-up interrupt on transfer events.

10. I2C reception and transmission is functional and autonomous in Stop mode and generates a wake-up interrupt on transfer

events.

11. SPI reception and transmission is functional and autonomous in Stop mode and generates a wake-up interrupt on transfer

events.

12. A/D conversion is functional and autonomous in Stop mode, and generates a wake-up interrupt on conversion events.

13. LPTIM is functional and autonomous in Stop mode, and generates a wake-up interrupt on events.

14. GPDMA transfers are functional and autonomous in Stop 0 mode, and generates a wake-up interrupt on transfer events.

15. DBGMCU remains accessible trough AP0.

16. DBGMCU remains accessible through AP0 when CDBGPWRUPREQ is set.

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