STM32WBA50KG datasheet(16/110 Pages) STMICROELECTRONICS

16 / 110 page

Functional overview

STM32WBA50KG

16/110

DS14688 Rev 1

JTAG/SWD interfaces are disabled. If the secret key was previously configured in

lower RDP levels, the device enables the RDP regression from Level 2 to Level 1

after password authentication through JTAG/SWD interface.

•

Write protection (WRP) to protect areas against erasing and programming. Two areas

can be selected with 8-Kbyte granularity.

The whole nonvolatile memory embeds the ECC (error correction code) feature supporting:

•

single-error detection and correction

•

double-error detection

•

ECC fail address report

3.6

Embedded SRAMs

SRAM1 and SRAM2 are the main SRAMs embedded in the devices, each with specific

features. Both can be used for peripherals background autonomous mode (BAM).

These SRAMs can be powered down in Stop mode to reduce consumption:

•

SRAM1: one 16-Kbyte block, can be retained in Standby mode

•

SRAM2: one 48-Kbyte block with parity, can be retained in Standby mode.

Table 3. Access status versus protection level and execution modes

Area

RDP

level

User execution

(boot from flash memory)

Debug/boot from RAM/bootloader(1)

Read

Write

Erase

Read

Write

Erase

Flash main memory

Yes

No(4)

Yes

N/A

System memory (2)

Yes

N/A

Option bytes(3)

1Yes

Yes(4)

N/A

Yes

Yes(4)

N/A

Yes

N/A

OTP

1Yes

Yes(5)

N/A

Yes

Yes(5)

N/A

2Yes

Yes(5)

N/A

Backup registers

Yes

N/A

N/A(6)

Yes

N/A

SRAM2

Yes

N/A

N/A(7)

Yes

N/A

1. When the protection level 2 is active, the debug port, the boot from RAM, and the boot from system memory are disabled.

2. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode.

3. Option bytes are accessible only through the flash memory interface registers and OPSTRT bit.

4. The flash main memory is erased when the RDP option byte changes from level 1 to level 0.

5. OTP can be written only once.

6. The backup registers are erased when RDP changes from level 1 to level 0.

7. All SRAMs are erased when RDP changes from level 1 to level 0.

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