STM32WBA50KG datasheet(15/110 Pages) STMICROELECTRONICS

15 / 110 page

DS14688 Rev 1

15/110

STM32WBA50KG

Functional overview

•

Power consumption intrinsically reduced (more accesses to cache memory rather than

to bigger main memories), even improved by configuring ICACHE as direct mapped

(rather than the default two-ways set-associative mode)

•

Maintenance operation for software management of cache coherency

•

Error management: detection of unexpected cacheable write access, with optional

interrupt raising

3.3

Memory protection unit

The MPU is used to manage the CPU accesses to the memory and to prevent tasks to

accidentally corrupt the memory or the resources used by other active tasks. This memory

area is organized into up to 8 protected areas.

The MPU is especially helpful for applications where some critical or certified code must be

protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-

time operating system). If a program accesses a memory location prohibited by the MPU,

the RTOS can detect it and take action. In an RTOS environment, the kernel can

dynamically update the MPU area setting based on the process to execute.

The MPU is optional and can be bypassed for applications that do not need it.

3.4

Multi-AHB bus matrix

A 32-bit multi-AHB bus matrix interconnects all the masters (CPU, GPDMA1) and the slaves

(flash memory, SRAMs, AHB, and APB) peripherals. It also ensures a seamless and

efficient operation even when several peripherals work simultaneously.

3.5

Embedded flash memory

The devices feature 1 Mbyte of embedded flash memory, available to store programs and

data. This memory supports 10000 cycles, and up to 100000 cycles on 32 pages

(256 Kbytes).

A 128-bit instruction prefetch is implemented and can optionally be enabled.

The flash memory contains 128 pages of 8 Kbytes, and embeds a 512-byte OTP (one time

programmable) for user data.

The configuration of flexible protections is possible thanks to the option bytes:

•

RDP (readout protection) to protect the whole memory, has four levels of protection

available (see Table 3):

–

Level 0: no readout protection

–

Level 1: memory readout protection

The flash memory cannot be read from or written to if either the debug features

are connected or the boot in SRAM or bootloader are selected. Regressions from

Level 1 to lower levels can be protected by password authentication.

–

Level 2: chip readout protection

The debug features, the boot in RAM and the bootloader selection are disabled. A

secret key can be configured to allow the regression capability from Level 2 to

Level 1. By default (key not configured), this Level 2 selection is irreversible and

STM32WBA50KG Datasheet(PDF) 15 Page - STMicroelectronics

STM32WBA50KG Datasheet(HTML) 15 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL