STM32WBA50KG datasheet(14/110 Pages) STMICROELECTRONICS

14 / 110 page

Functional overview

STM32WBA50KG

14/110

DS14688 Rev 1

Functional overview

3.1

Arm Cortex-M33 core with MPU, DSP, and FPU

The Cortex-M33 with MPU, DSP and FPU is a highly energy-efficient processor designed

for microcontrollers and deeply embedded applications.

The Cortex-M33 processor delivers a high computational performance with low-power

consumption and an advanced response to interrupts. It features:

•

MPUs (memory protection units), supporting up to 8 regions for applications

•

Floating-point arithmetic functionality, with support for single precision arithmetic

The processor supports a set of DSP instructions for efficient signal processing and

complex algorithm execution.

The Cortex-M33 processor supports the following bus interfaces:

•

System AHB (S-AHB) bus: used for instruction fetch and data access to the memory-

mapped SRAM, peripheral, and Vendor_SYS regions of the Armv8-M memory map.

•

Code AHB (C-AHB) bus: used for instruction fetch and data access to the code region

of the Armv8-M memory map.

3.2

ART Accelerator (ICACHE)

The ICACHE (instruction cache) is introduced on C-AHB code bus of Cortex-M33 processor

to improve performance when fetching instruction (or data) from internal memories.

ICACHE offers the following features:

•

Multi-bus interface:

–

Slave port receiving the memory requests from the Cortex-M33 C-AHB code

execution port

–

Master1 port performing refill requests to internal flash memory

–

Master2 port performing refill requests to internal SRAMs

–

Second slave port dedicated to ICACHE registers access

•

Close to 0 wait-states instructions/data access performance:

–

0 wait-state on cache hit

–

Hit-under-miss capability, allowing to serve new processor requests while a line

refill (due to a previous cache miss) is still ongoing

–

Critical-word-first refill policy, minimizing processor stalls on cache miss

–

Hit ratio improved by two-ways set-associative architecture and pLRU-t

replacement policy (pseudo-least-recently-used, based on binary tree), algorithm

with best complexity/performance balance

–

Dual master ports to decouple internal flash memory and SRAM traffic, on fast and

slow buses, respectively; also minimizing impact on interrupt latency

–

Optimal cache line refill thanks to AHB burst transactions (of the cache line size)

–

Performance monitoring by means of a hit counter and a miss counter

•

Extension of cacheable region beyond the code memory space, by means of address

remapping logic enabling the definition of four regions

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