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STM32WBA50KG Datasheet(PDF) 84 Page - STMicroelectronics

Part # STM32WBA50KG
Description  Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M33 with FPU, Bluetooth® 5.4 radio solution
PDF  110 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32WBA50KG Datasheet(HTML) 84 Page - STMicroelectronics

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Electrical characteristics
STM32WBA50KG
84/110
DS14688 Rev 1
Static latch-up
The following complementary static tests are required on three parts to assess the latch-up
performance:
•
a supply overvoltage is applied to each power supply pin
•
a current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
5.3.15
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3.3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller if
abnormal injection accidentally happens, some susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed, the device is stressed by injecting current into the
I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at
a time, the device is checked for functional failures.
The failure is indicated by an out-of-range parameter, such as an ADC error above a certain
limit (higher than 5 LSB ET), out of conventional limits of induced leakage current on
adjacent pins (out of the -5 µA / 0 µA range) or other functional failure (for example reset
occurrence or oscillator frequency deviation).
The characterization results are given in Table 60. The negative/positive induced leakage
current is caused by the negative/positive injection.
5.3.16
I/O port characteristics
General input/output characteristics
The parameters given in Table 61 are derived from tests performed at ambient temperature
and under the supply voltage conditions summarized in Table 26. All I/Os are designed as
CMOS- and TTL-compliant.
Table 59. Electrical sensitivity(1)
1. Evaluated by characterization, not tested in production, unless otherwise specified.
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
TJ = 130 °C conforming to JESD78E
2
Table 60. I/O current injection susceptibility(1)
1. Evaluated by characterization, not tested in production, unless otherwise specified.
Symbol
Description
Functional susceptibility
Unit
Negative injection
Positive injection
IINJ
Injected current on all pins
5
N/A
mA



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