STM32WBA50KG datasheet(97/110 Pages) STMICROELECTRONICS

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DS14688 Rev 1

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STM32WBA50KG

Electrical characteristics

103

5.3.25

I2C interface characteristics

The I2C interface meets the timings requirements of the I2C-bus specification and user

manual rev. 03 for:

•

Standard-mode (Sm): bit rate up to 100 kbit/s

•

Fast-mode (Fm): bit rate up to 400 kbit/s

•

Fast-mode Plus (Fm+): bit rate up to 1 Mbit/s.

The I2C timings are valid when the I2C peripheral is properly configured (see the reference

manual).

The SDA and SCL I/O requirements are met with the following restriction: the SDA and SCL

I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected

between the I/O pin and VDD is disabled, but is still present. I2C SDA and SCL use I/O FT

structure with _f option supporting Fm+ low-level output-current maximum requirement.

Refer to Section 5.3.16 for I2C I/O characteristics.

All I2C SDA and SCL I/Os embed an analog filter, refer to Table 76 for its characteristics.

1. The exact timings depend upon the phasing of the APB interface clock vs. the IWDG kernel clock, hence there is always a

full kernel clock period of uncertainty.

2. Specified by design, not tested in production.

Table 75. WWDG min/max timeout value at 100 MHz (PCLK)

Prescaler divider

WDGTB[2:0]

Min timeout value

Max timeout value

Unit

0.040

1.621

0.081

5.242

0.163

10.485

0.327

20.971

/16

0.655

41.943

/32

1.310

83.886

/64

2.621

167.772

/128

5.242

335.544

Table 76. I2C analog filter characteristics(1)

1. Specified by design, not tested in production.

Symbol

Parameter

Min

Max

Unit

tAF

Maximum pulse width of spikes suppressed by the analog filter

50(2)

2. Spikes with widths below tAF min are filtered.

190(3)

3. Spikes with widths above tAF max are not filtered.

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