STM32WBA50KG datasheet(45/110 Pages) STMICROELECTRONICS

45 / 110 page

DS14688 Rev 1

45/110

STM32WBA50KG

Functional overview

The I2C peripheral supports:

•

I2C-bus specification and user manual rev. 5 compatibility:

–

Slave and Master modes, multi-master capability

–

Standard-mode (Sm), with a bit rate up to 100 Kbit/s

–

Fast-mode (Fm), with a bit rate up to 400 Kbit/s

–

Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s and 20 mA output drive I/Os

–

7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

–

Programmable setup and hold times

–

Optional clock stretching

•

System management bus (SMBus) specification rev 3.0 compatibility:

–

Hardware packet error checking (PEC) generation and verification with ACK

control

–

Address resolution protocol (ARP) support

–

SMBus alert

•

Power system management protocol (PMBus) specification rev 1.3 compatibility

•

Independent clock: a choice of independent clock sources allowing the I2C

communication speed to be independent from the PCLK reprogramming

•

Autonomous functionality in Stop modes with wake-up from Stop capability

•

Programmable analog and digital noise filters

•

1-byte buffer with DMA capability

3.27

Universal synchronous/asynchronous receiver transmitter

(USART/UART) and low-power universal asynchronous

receiver transmitter (LPUART)

The devices have one embedded universal synchronous receiver transmitter (USART1) and

one low-power universal asynchronous receiver transmitter (LPUART1).

Table 15. I2C implementation

I2C features(1)

1. X: supported

I2C3

Standard-mode (up to 100 Kbit/s)

Fast-mode (up to 400 Kbit/s)

Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)

Programmable analog and digital noise filters

SMBus/PMBus hardware support

Independent clock

Autonomous in Stop modes with wake-up capability

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