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STM32WBA50KG Datasheet(PDF) 31 Page - STMicroelectronics

Part # STM32WBA50KG
Description  Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M33 with FPU, Bluetooth® 5.4 radio solution
PDF  110 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32WBA50KG Datasheet(HTML) 31 Page - STMicroelectronics

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STM32WBA50KG
Functional overview
50
The GPIO allows dynamic I/O control in Stop 0 mode thanks to GPDMA1. All I/Os can be
configured and controlled as input or output (open-drain or push-pull depending on GPIO
configuration).
When enabled in the PWR, latest I/Os output level can be retained by pulling the I/Os high
or low before entering Standby mode. I/O levels are retained after exit from Standby mode,
until they are reconfigured by software.
3.12
System configuration controller (SYSCFG)
The main purpose of the SYSCFG (system configuration controller) are the following:
•
Managing robustness features
•
Configuring FPU interrupts
•
Enabling/disabling the I2C fast-mode plus high-drive mode of some I/Os and booster
for I/Os analog switches
•
Managing the I/O compensation
•
Provides memory erase status
3.13
Peripheral interconnect matrix
Several peripherals have direct connections between them, to have autonomous
communication between them and to support the saving of CPU resources (thus power
supply consumption). In addition, these hardware connections allow fast and predictable
latency.
Depending on the peripherals, these interconnections can operate in Run, Sleep and Stop
modes.
3.14
General purpose direct memory access controller (GPDMA)
This controller is a bus master and system peripheral.
The GPDMA is used to perform programmable data transfers between memory-mapped
peripherals and/or memories via linked-lists, upon the control of an off-loaded CPU.
The GPDMA main features are:
•
Dual bidirectional AHB master
•
Memory-mapped data transfers from a source to a destination:
–
Peripheral-to-memory
–
Memory-to-peripheral
–
Memory-to-memory
–
Peripheral-to-peripheral
•
Autonomous data transfers during Run, Sleep and Stop 0 modes
•
Transfers arbitration based on a four-grade programmed priority at a channel level:
–
One high-priority traffic class, for time-sensitive channels (queue 3)
–
Three low-priority traffic classes, with a weighted round-robin allocation for non
time-sensitive channels (queues 0, 1, 2)



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