STM32WBA50KG datasheet(24/110 Pages) STMICROELECTRONICS

24 / 110 page

Functional overview

STM32WBA50KG

24/110

DS14688 Rev 1

By default, the microcontroller is in Run mode after a system or a power on reset. It is up to

the user to select one of the low-power modes described below:

•

Sleep

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt or event occurs.

•

Stop 0 and Stop 1

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the HSI16,

and the HSE32 crystal oscillators are disabled. The LSE or LSI is still running.

The RTC, TAMP, IWDG and SLEEP_TIMER can remain active.

Some peripherals are autonomous and can operate in Stop mode by requesting their

kernel clock and their bus clock when needed, in order to transfer data with DMA Stop

0 modes will be entered. Refer to Background autonomous mode (BAM) for more

details. In Stop modes the bus clocks when requested use HSI16.

Stop 0 offer the largest number of active peripherals, with or without DMA, and wake-up

sources, a smaller wake-up time but a higher consumption than Stop 1.

In Stop 0 mode, the main regulator remains ON, allowing a very fast wake-up time, but

with much higher power consumption.

Stop 1 is the lowest power mode with full retention, but the functional peripherals and

sources of wake-up are reduced.

The BOR can be configured in ultra-low power mode to further reduce power

consumption during Stop 1 mode.

The system clock when exiting from Stop 0 or Stop 1 modes is HSI16.

•

Standby retention and Standby

The Standby mode is used to achieve the lowest power consumption. The internal

regulator is switched off so that the VCORE domain is powered off. The PLL, the HSI16

and the HSE32 crystal oscillators are also switched off. The LSE or LSI is still running.

The RTC and IWDG can remain active.

The BOR always remains active in Standby mode.

The BOR can be configured in ultra-low power mode to further reduce power

consumption during Standby mode.

The state of each I/O during Standby mode can be retained with internal pull-up,

internal pull-down or floating.

After entering Standby mode, SRAMs and register contents are lost except for registers

in the Backup domain and Standby circuitry. Optionally, the full SRAM1 and/or SRAM2

can be retained in Standby mode, supplied by the low-power regulator (Standby with

RAM retention mode). Also optionally the 2.4 GHz RADIO can be retained in Standby

mode, supplied by the low-power regulator (Standby with 2.4 GHz RADIO retention

mode).

The device exits Standby modes when an external reset (NRST pin), an IWDG event or

reset, WKUP pin event (configurable rising or falling edge), an RTC event occurs

(alarm, periodic wake-up, timestamp), or a tamper detection. The tamper detection can

be raised either due to external pins or due to an internal failure detection.

When in Standby with 2.4 GHz RADIO retention mode also the SLEEP_TIMER can exit

the device from Standby mode.

The system clock after wake-up is HSI16.

STM32WBA50KG Datasheet(PDF) 24 Page - STMicroelectronics

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