STM32WBA50KG datasheet(23/110 Pages) STMICROELECTRONICS

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Standby

retention

LPR

OFF

ON(5)

LSE

LSI

BOR, RTC, TAMP, IWDG,

SLEEP_TIMER

All other peripherals are powered off.

I/O configuration can be retained,

floating, pull-up or pull-down.

Reset pin,

WKUPx (x = 1, 3, 4, 6, 7, 8),

BOR, RTC, TAMP, IWDG, SLEEP_TIMER

Standby

OFF

All from mode Standby retention, except SLEEP_TIMER

1. LPR means that the main regulator is OFF and the low-power regulator is ON.

2. All peripherals can be active or clock gated to save power consumption.

3. The flash memory can be put in power-down and its clock can be gated off when executing from SRAM.

4. The SRAM1 and SRAM2 clocks can be gated on or off independently.

5. The SRAM can be individually powered off to save power consumption.

6. HSI16 can be temporary enabled upon peripheral request, for autonomous functions with DMA or wake-up from Stop event detections.

7. The ADC conversion is functional and autonomous with DMA in Stop 0 mode, and can generate a wake-up interrupt on conversion events.

8. U(S)ART and LPUART transmission and reception is functional and autonomous with DMA in Stop 0 mode, and can generate a wake-up interrupt on transfer

events.

9. SPI transmission and reception is functional and autonomous with DMA in Stop 0 mode, and can generate a wake-up interrupt on transfer events.

10. I2C transmission and reception is functional and autonomous with DMA in Stop 0 mode, and can generate a wake-up interrupt on transfer events.

11. LPTIM is functional and autonomous with DMA in Stop 0 mode, and can generate a wake-up interrupt on all events.

12. GPDMA is functional and autonomous in Stop 0 mode, and can generate a wake-up interrupt on events.

13. Active peripherals ADC, U(S)ART, LPUART, SPI, I2C and LPTIM, can generate bus clock request and/or a wake-up interrupt on event.

Table 6. Operating modes overview (continued)

Mode

Regulator(1) CPU

Flash

memory

SRAM

Clocks

DMA and peripherals(2)

Wake-up source

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