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STM32WBA50KG Datasheet(PDF) 30 Page - STMicroelectronics |
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STM32WBA50KG Datasheet(HTML) 30 Page - STMicroelectronics |
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30 / 110 page  Functional overview STM32WBA50KG 30/110 DS14688 Rev 1 Figure 5. Clock tree 3.11 General-purpose input/output (GPIO) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. After reset, all GPIOs are in analog mode to reduce power consumption. The I/Os alternate function configuration can be locked, if needed, following a specific sequence in order to avoid spurious writing to the I/Os registers. LSE OSC 32.768 kHz or 32.000 kHz LSCO to IWDG HSE OSC 32 MHz HSE CSS OSC_IN OSC_OUT HSI16 RC 16 MHz MCO /1 - 16 /32 LSE CSS /1000 PLL1 /P /Q /M SYSCLK HSI16 HSI16 HSE32 HSE32 pll1rclk pll1rclk LSE LSI sysclkpre HSI16 HSE32PRE hclk1 APB1 PPRE1 /1,2,4,8,16 to CPU, AHB1, AHB2, Flash, SRAM1 to CPU FCLK /8 to CPU system timer pclk1 pclk2 to TIM2 to TIM1, 16, 17 to LPTIM1 kernel to ADC4 kernel to RTC and TAMP x1 or x2 x1 or x2 HSI16 HSI16 pclk7 LSI LSE pll1pclk SYSCLK pclk7 LSE to 2.4 GHz RADIO sleep timer hclk5 to AHB5 to APB2 to APB1 to 2.4 GHz RADIO RF hclk1 to RNG kernel pll1qclk pll1rclk OSC32_IN OSC32_OUT LSI LSE LSE xN LSI LSE HSI16 HSE32 HSI16 SYSCLK pclk2 LSE LSI LSE APB7 PPRE7 /1,2,4,8,16 pclk7 to APB7 SYSCLK HSI16 pll1pclk pll1qclk to SPI3 kernel pclk7 HSI16 pll1pclk pll1qclk to AHB4 APB2 PPRE2 /1,2,4,8,16 SYSCLK /2 HSE32 HSE_RF HPRE /1,2,4,8,16 LSI HSEPRE /1, 2 HPRE5 /1,2,3,4,6 HDIV5 /1,2 /R to 2.4 GHz RADIO kernel EN PLLRPRE SW, SWS system clock source control ref_ck hclk5 to LPUART1 kernel to UART1 kernel to I2C3 kernel pclk7 SYSCLK HSI16 LSI1 RC ~32 kHz /1, 128 |
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