STM32WBA50KG datasheet(38/110 Pages) STMICROELECTRONICS

38 / 110 page

Functional overview

STM32WBA50KG

38/110

DS14688 Rev 1

•

Has an AHB slave peripheral, accessible through 32-bit word single accesses only

(else an AHB bus error is generated, and the write accesses are ignored)

3.20

Advanced encryption standard hardware accelerator (AES)

The devices embed one AES accelerator (AES).

The AES can be used to encrypt and decrypt data using the AES algorithm. It is a fully

compliant implementation of the advanced encryption standard (AES) as defined by Federal

Information Processing Standards Publication (FIPS PUB 197, Nov 2001).

Multiple chaining modes are supported for key sizes of 128 or 256 bits. ECB, CBC, CTR,

CCM, GCM and GMAC chaining are supported.

The AES supports DMA single transfers for incoming and outgoing data (two DMA channels

required).

The AES supports the selection of the 256-bit software key, written by the application in the

key registers (write only).

Note:

128-bit key size can also be selected.

The peripheral supports:

•

Compliant implementation of standard NIST Special Publication 197, Advanced

Encryption Standard (AES) and Special Publication 800-38A, Recommendation for

Block Cipher Modes of Operation

•

128-bit data block processing

•

Support for cipher keys length of 128-bit and 256-bit

•

Encryption and decryption with multiple chaining modes:

–

Electronic codebook (ECB) mode

–

Cipher block chaining (CBC) mode

–

Counter (CTR) mode

–

Galois counter mode (GCM)

–

Galois message authentication code (GMAC) mode

–

Counter with CBC-MAC (CCM) mode

•

51 or 75 clock cycle latency in ECB encryption mode for AES processing one 128-bit

block of data with, respectively, 128- or 256-bit key

•

Integrated round key scheduler to compute the last round key for AES ECB/CBC

decryption

•

256-bit register for storing the cryptographic key (four 32-bit registers), with key

atomicity enforcement

•

128-bit registers for storing initialization vectors (four 32-bit registers)

•

One 32-bit input buffer and one 32-bit output buffer

•

Automatic data flow control with support of single-transfer direct memory access (DMA)

using two channels (one for incoming data, one for processed data)

•

Data swapping logic to support 1-, 8-, 16- or 32-bit data

•

Possibility for software to suspend a message if the AES needs to process another

message with a higher priority (suspend/resume operation)

STM32WBA50KG Datasheet(PDF) 38 Page - STMicroelectronics

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