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STM32WBA50KG Datasheet(PDF) 103 Page - STMicroelectronics |
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STM32WBA50KG Datasheet(HTML) 103 Page - STMicroelectronics |
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103 / 110 page ![]() DS14688 Rev 1 103/110 STM32WBA50KG Electrical characteristics 103 Figure 25. JTAG timing diagram Figure 26. SWD timing diagram Table 80. SWD characteristics(1) 1. Evaluated by characterization, not tested in production. Symbol Parameter Conditions Min Typ Max Unit fSWCLK 1/tc(SWCLK) SWCLK clock frequency 2.7 V ≤ VDD ≤ 3.6 V - - 62.5 MHz 1.71 V ≤ VDD < 2.7 V - - 34 tisu(SWDIO) SWDIO input setup time - 1 - - ns tih(SWDIO) SWDIO input hold time - 2.5 - - tov(SWDIO) SWDIO output valid time 2.7 V ≤ VDD ≤ 3.6 V - 12 16 1.71 V ≤ VDD < 2.7 V - 12 29 toh(SWDIO) SWDIO output hold time - 8.5 - - MSv40458V1 TDI/TMS TCK TDO tc(TCK) tw(TCKL) t w(TCKH) th(TMS/TDI) tsu(TMS/TDI) tov(TDO) toh(TDO) MSv40459V1 SWDIO SWCLK SWDIO tc(SWCLK) twSWCLKL) tw(SWCLKH) th(SWDIO) tsu(SWDIO) tov(SWDIO) toh(SWDIO) (receive) (transmit) |
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