SN8F5708 datasheet(59/204 Pages) SONIX

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SN8F5708 Series

Interrupt

Datasheet Rev. 2.4

10.1

Interrupt Operation

Interrupt operation is controlled by interrupt request flag and interrupt enable bits. Interrupt

request flag is interrupt source event indicator, no matter what interrupt function status (enable or

disable). Both interrupt enable bit and global interrupt (EAL=1) are enabled, the system executes

interrupt operation when each of interrupt request flags actives. The program counter points to

interrupt vector (0x03 – 0xEB) and execute ISR.

10.2

Interrupt Priority

Each interrupt source has its specific default priority order. If two interrupts occurs simultaneously,

the higher priority ISR will be service first. The lower priority ISR will be serviced after the higher

priority ISR completes. The next ISR will be service after the previous ISR complete, no matter the

priority order.

For special priority needs, 4-level priority levels (Level 0 – Level 3) are used. All interrupt sources

are classified into 6 priority groups (Group0 – Group5). Each group can be set one specific priority

level. Priority level is selected by IP0/IP1 registers. Level 3 is the highest priority and Level 0 is the

lowest. The interrupt sources inside the same group will share the same priority level. With the

same priority level, the priority rule follows default priority.

Priority Level

IP1.x

IP0.x

Level 0

Level 1

Level 2

Level 3

The ISR with the higher priority level can be serviced first; even can break the on-going ISR with

the lower priority level. The ISR with the lower priority level will be pending until the ISR with the

higher priority level completes.

Group

Interrupt Source

Group 0

INT0

PWM1

I2C

Group 1

Timer 0

PWM2

SPI

Group 2

INT1

PWM3

T2COM0

Group 3

Timer 1

ADC

T2COM1

Group 4

UART

Comparator 0

T2COM2

Group 5

Timer 2

Comparator 1

INT2

T2COM3

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