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SN8F5708 Datasheet(PDF) 67 Page - SONiX Technology Company |
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SN8F5708 Datasheet(HTML) 67 Page - SONiX Technology Company |
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67 / 204 page ![]() www.sonix.com.tw SN8F5708 Series Copyright © 2019, SONiX Technology Co., Ltd. Interrupt Datasheet Rev. 2.4 67 S0CON Register (0X98) Bit Field Type Initial Description 1 TI0 R/W 0 UART transmit interrupt request flag. It indicates completion of a serial transmission at UART. It is set by hardware at the end of bit 8 in mode 0 or at the beginning of a stop bit in other modes. It must be cleared by software. 0: None UART transmit interrupt request. 1: UART transmit interrupt request. 0 RI0 R/W 0 UART receive interrupt request flag. It is set by hardware after completion of a serial reception at UART. It is set by hardware at the end of bit 8 in mode 0 or in the middle of a stop bit in other modes. It must be cleared by software. 0: None UART receive interrupt request. 1: UART receive interrupt request. Else Refer to other chapter(s) SPSTA Register (0XE1) Bit Field Type Initial Description 7 SPIF R 0 SPI complete communication flag Set automatically at the end of communication Cleared automatically by reading SPSTA, SPDAT registers 4 MODF R 0 Mode fault flag Else Refer to other chapter(s) I2CCON Register (0XDC) Bit Field Type Initial Description 7 SI R/W 0 Serial interrupt flag The SI is set by hardware when one of 25 out of 26 possible I2C states is entered. The only state that does not set the SI is state F8h, which indicates that no relevant state information is available. The SI flag must be cleared by software. In order to clear the SI bit, ‘0’ must be written to this bit. Writing a ‘1’ to SI bit does not change value of the SI. Else Refer to other chapter(s) |
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