SN8F5708 datasheet(94/204 Pages) SONIX

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SN8F5708 Series

Timer 2

Datasheet Rev. 2.4

IEN1

ET2RL

ET2C3

ET2C2

ET2C1

ET2C0

ESPI

EI2C

IRCON

TF2RL

TF2

TF2C3

TF2C2

TF2C1

TF2C0

T2CON Register (0xC8)

Bit

Field

Type

Initial

Description

T2PS

R/W

Timer 2 pre-scalar

0: fcpu/12

1: fcpu/24

I3FR

R/W

In compare mode:

0: The COM0 interrupt would be generated when the

TH2/TL2 becomes not equal to the CRC register (e.g.

Timer 2: 0x8081, CRC: 0x8080).

1: The COM0 interrupt would be generated when the

TH2/TL2 becomes equal to the CRC register.

In capture mode 0:

0: The timer 2 content would be latched into CRC

1: The timer 2 content would be latched into CRC

Reserved

R/W

4..3

T2R[1:0]

R/W

Specified Timer 2 reload value

00: Disable

01: Disable

10: Load CRCH/CRCL to TH2/TL2 by counter overflow

11: Load CRCH/CRCL to TH2/TL2 by T2RL pin

T2CM

R/W

Timer 2 comparison output

0: Directly output method

1: Indirectly output, next output status can be specified

1..0

T2I[1:0]

R/W

Timer 2 up counting control

00: Disable

01: Clock rate is defined by T2PS

10: Clock source is T2 pin

11: Clock rate is defined by T2PS with T2 pin gate control

SN8F5708 Datasheet(PDF) 94 Page - SONiX Technology Company

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