SN8F5708 datasheet(70/204 Pages) SONIX

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SN8F5708 Series

MDU

Datasheet Rev. 2.4

CPU cycles depends on the shift time.

In normalizing operation, the 32-bit unsigned integer would be shifted left repeatedly until the

most significant bit (7

th bit of MD3 register) is 1. A normalizing operation takes 4 to 19 CPU cycles

depends on the actual shift time.

Both shifting and normalizing operations are started by proper sequence of writing registers: MD0,

MD1, MD2, MD3, and finally ARCON register. The result would be place in MD0 to MD3 registers

which should be read in the sequence of MD0, MD1, MD2, and MD3.

11.4

Cooperate with Keil C51

Because Keil C51 supports both of hardware and software multiplication/division operators, a

command line ‘#pragma mdu_r515’ is required in C to enable the hardware MDU functionality for

higher performance. Subsequently, Keil C51 would compile mathematic operators with MDU

support.

#include <SN8F5708.H>

#pragma mdu_r515

//Keil C51 MDU command line

11.5

The Error Flag (MDEF)

The “MDEF” error flag indicates an improperly performed operation (when one of the arithmetic

operations has been restarted or interrupted by a new operation). The error flag mechanism is

automatically enabled with the first write operation to “MD0” and disabled with the final read

instruction from “MD3” (multiplication or shift/normalize) or “MD5” (division) in phase three.

The error flag is set when:

There is a write access to ‘MDx’ registers (any of ’MD0’ to ‘MD5’ and ARCON ) during phase two of

MDU operation (restart or calculations interrupting)

There is a read access to one of MDx registers during phase two of MDU operation when the error

flag mechanism is enabled. In such condition error flag is set but the calculation is not interrupted.

The error flag is reset only after read access to “ARCON” register. The error flag is read only.

11.6

The Overflow Flag (MDOV)

The MDOV overflow flag is set when one of the following conditions occurs:

Division by zero

Multiplication with a result greater than 0000 FFFFh

Start of normalizing if the most significant bit of MD3 is set (MD3.7= 1)

Any operation of the MDU that does not match the above conditions clears the overflow flag. Note

that the overflow flag is exclusively controlled by hardware. It cannot be written.

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